Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing permissible functions of output gates and remaining gates
AssigneeFujitsu Limited
InventorYusuke Matsunaga
Life of this patent
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Abstract
A method of automatically forming a combinational LSI circuit comprising two processes. A first process of computing the permissible function of each element (gate) of a given circuit. A second process of connecting a gate having a shorter signal propagation time to a gate located on a path that does not satisfy a prescribed delay time and removing the gate from the path. Thus, an arrangement of the circuit is changed and the maximum delay time of the circuit is suppressed below the prescribed delay time. This method efficiently shortens the delay time of the combinational circuit to satisfy the prescribed delay time.
Claims4
A method of automatically designing an LSI combinational circuit using a computer, comprising:
- (a) computing a permissible function of output gates in an initial circuit;
- (b) selecting one of the output gates whose permissible functions have been computed in step (a);
- (c) computing permissible functions of all inputs of the output gate selected in step (b);
- (d) computing a permissible function of each input gate of the output gate selected in the step (b);
- (e) computing permissible functions of the remaining gates in the initial circuit;
- (f) computing path delay of circuit paths of the initial circuit;
- (g) selecting a path gate located on a circuit path that does not satisfy a prescribed delay time;
- (h) performing one of:
- (1) deleting the selected path gate;
- and
- (2) adding an additional path gate and deleting the selected path gate to change an arrangement of the initial circuit to satisfy the prescribed delay time.
A method of automatically designing an LSI combinational circuit using a computer comprising:
- (a) computing a permissible function for each gate of an initial circuit;
- (b) computing path delay of circuit paths of the initial circuit;
- (c) selecting a path gate located on a circuit path that does not satisfy a prescribed delay time;
- (d) detecting gates in the initial circuit whose signal propagation time is longer than a prescribed delay time;
- (e) selecting as a target gate one of the gates detected in step (d) located closer to an output of the initial circuit;
- and
- (f) performing a delay time shortening process by performing one of:
- (i) deleting the target gate;
- and
- (ii) adding another gate and deleting the target gate and the permissible function of the target gate is maintained, thereby shortening a signal propagation time.
Dependencies are inferred from the claim text.