Late cancel method and apparatus for a high performance microprocessor system

In a microprocessor system comprising a processor, an external cache memory coupled to said processor through a backside bus, a main memory, wherein said processor includes an instruction fetch unit, an instruction decoder, an external bus controller, an internal cache memory, a pipe sequencer, an execution unit, and external cache hit or miss logic, a method for obtaining and processing a desired instruction comprising the steps of:

• (a) said instruction fetch unit coupling a request for a desired instruction to said external bus controller;
• (b) said external bus controller responsively accessing said external cache memory over said backside bus;
• (c) said external cache memory responsively coupling a cache word and cache tag to said backside bus;
• (d) said instruction fetch unit reading said cache word from said backside bus;
• (e) said external bus controller reading said cache tag from said backside bus, said external bus controller providing said cache tag to said external cache hit or miss logic;
• (f) said instruction fetch unit pre-decoding said cache word as an instruction, while concurrently, said cache hit or miss logic determines whether said cache word is a valid instruction;
• (g) said instruction decoder decoding said cache word;
• (h) if said cache hit or miss logic determines said cache word is a valid instruction, said execution unit executing said cache word as a valid instruction;
• (i) if said cache hit or miss logic determines said cache word is an invalid instruction, said instruction fetch unit canceling the execution of said cache word as an invalid instruction;
• (i.1) if said cache word is an invalid instruction said external bus controller coupling a request for said desired instruction to said main memory;
• (i.2) if said cache word is an invalid instruction said main memory responsively coupling said desired instruction to said instruction fetch unit.

A processor system comprising:

• processor means;
• external cache memory means coupled to said processor means;
• main memory means coupled to said processor means;
• wherein said processor means includes:
• an instruction execution unit;
• concurrent processing and determination means for processing a cache word provided to said processor means from said external cache memory means in response to a processor means request for a desired instruction coupled to said external cache memory means, while concurrently with said processing, determining whether said cache word is valid;
• decoding means for further processing said cache word and preparing to couple said desired instruction to said instruction execution unit;
• late cancel means for canceling the execution of said cache word in the event said concurrent processing and determination means determines that said cache word is invalid.

A processor system comprising:

• a processor;
• an external cache memory coupled to said processor;
• main memory coupled to said processor;
• wherein said processor includes:
• an instruction execution unit;
• concurrent processing and determination means for processing a cache word provided to said processor from said external cache memory in response to a processor request for a desired instruction coupled to said external cache memory, while concurrently with said processing, determining whether said cache word is valid;
• decoding means for further processing said cache word and preparing to couple said desired instruction to said instruction execution unit;
• late cancel means for canceling the execution of said cache word in the event said concurrent processing and determination means determines that said cache word is invalid.

A processor comprising:

• bus means for coupling said processor to an external instruction cache;
• an instruction execution unit;
• concurrent processing and determination means for processing a cache word provided to said processor over said bus means from said external instruction cache memory, while concurrently with said processing, determining whether said cache word is valid;
• decoding means for further processing said cache word and preparing to couple said desired instruction to said instruction execution unit;
• selective late cancel means for canceling the execution of said cache word in the event said concurrent processing and determination means determines that said cache word is invalid and allowing said cache word to be executed in the event said concurrent processing and determination means determines that said cache word is valid.

A processor comprising:

• an instruction fetch unit;
• an instruction decode unit coupled to said instruction fetch unit capable of clearing stored information resulting from an instruction in response to a late cancel signal;
• an execution unit coupled to said decode unit;
• a pipe sequencer coupled to said instruction fetch unit;
• a backside bus coupled to said instruction fetch unit;
• external cache hit or miss logic coupled to said instruction fetch unit for concurrently determining whether a cache word provided over said backside bus to said instruction fetch unit from an external instruction cache is a valid instruction while said instruction fetch unit concurrently pre-decodes said cache word, said external cache hit or miss logic generating said late cancel signal if said cache word is not a valid instruction.