Dual cache memory device with cache monitoring

A dual cache memory device for use in a CPU (central processor unit) connected to a memory bus of a memory unit in which at least two module programs are stored, each of which module programs includes module instructions, module data to be processed by the module instructions, and a module header locating the module data which is stored in a location following the module header, comprising:

• processing means for performing arithmetic and logical operations with module data of the module programs, and performing arithmetic and logical operations with the module header of a second one of the module programs following execution of a first module program to prepare for processing defined by the second module program;
• pipeline instruction control means oeprative in pipelining for decoding the module instructions, executing processing defined by decoded module instructions, and controlling said processing means in response to decoded module instructions;
• instruction cache memory means connected to the memory bus through a bus controller and said pipeline instruction control means for storing therein the module header and the module instructions;
• operand cache memory means connected to the memory bus through said bus controller and said processing means for storing therein the module data;
• a header bus for connecting said instruction cache memory means to said processing means and conveying a block of module instructions from said instruction cache memory means to said processing means;
• and
• cache monitoring means connected to said instruction cache memory means, said operand cache memory means and said bus controller for monitoring said operand cache memory means to determine whether or not the module data is stored in said operand cache memory means, and further monitoring said instruction cache memory means to determine whether or not a block of module instructions is stored in said instruction cache memory means to control said instruction cache memory means, said operand cache memory means and said bus controller;
• said cache monitoring means controlling, when module data is not stored in said operand cache memory means, said bus controller and said operand cache memory means to read out module data for arithmetic and logic operations included in the module program from the memory unit to transfer said processing means the module data read out to said operand cache memory means;
• said cache monitoring means controlling, when a block of module instructions is not stored in said instruction cache memory means, said bus controller and said instruction cache memory means to read out a module header of a module program and a block of module instructions following the module header from the memory unit to transfer to said processing means over said header bus the block of module instructions read out to said instruction cache memory means.