Interlock for controlling processor ownership of pipelined data for a store in cache

Ownership change control for data units in a cache shared by a plurality of processors in a data processing system, in which the processors can independently execute different instruction streams, the ownership change control comprising:

• each processor of the plurality of processors having a private cache for receiving stores generated by an associated processor's instruction stream;
• a plurality of processor store pipelines for storing data into the shared cache generated by the processor instruction streams, each store pipeline associated with a respective one of the processors, each pipeline containing a plurality of pipeline entries for receiving data from a respective processor to be stored into addressed locations in data units in the shared cache, each entry in a pipeline being capable of holding an address and data to be stored in a data unit in the shared cache;
• an ownership indication for each data unit in the shared cache for identifying any processor having exclusive ownership of valid data stored in a data unit in the shared cache while the data unit is allowed to be changed by a processor indicated as having exclusive ownership;
• pipeline requesting means to request the shared cache to store data from an oldest entry in each pipeline into a data unit in the shared cache, a newest entry and an oldest entry in each pipeline being pipeline entries containing data most recently received and least recently received, respectively, by the pipeline;
• a shared cache controller for signalling to a processor identified as owning a requested data unit in the shared cache when the pipeline of an other processor requests to store data in the requested data unit in the shared cache, the processor providing a response signal for indicating if the pipeline associated with the processor does or does not contain store data for the requested data unit;
• the shared cache controller immediately changing the exclusive ownership identification of the requested data unit from the processor to the other processor to allow immediate store access of the requested data unit by the pipeline of the other processor;
• and,
• each processor executing instructions that put stores in an associated pipeline simultaneously while the shared cache controller is processing an ownership change for a prior store in any of the pipelines.