Logical-to-real address translation based on selective use of first and second TLBs

An information processing apparatus for accessing a cache memory by defining an address at an earlier stage, comprising:

• an instruction register for holding a base register identifier, an index register identifier, and displacement bits;
• a general-purpose register connected to said instruction register, for holding a content of a base register and a content of an index register, which have been designated by said base register identifier and said index register identifier;
• a logical address generator connected to said general-purpose register, for generating a logical address having both of a page address and a page offset based upon contents of said base register and said index register and said displacement bits;
• a logical address register connected to said logical address generator, for holding said page address and said page offset of said logical address;
• a selection controller for supplying a selection signal when any one of contents of said base register and also said index register corresponds to zero:
• a selecting circuit connected to said general purpose register and said logical address register, for supplying a selected one of a first output of said logical address generator and a second output of said general-purpose register in response to said selection signal derived from said selection controller;
• a translation look aside buffer connected to said selecting circuit, for receiving a selected output of said selecting circuit to supply a real address corresponding to said selected output of said selecting circuit;
• and
• a cache memory means connected to said translation look aside buffer, for performing a memory access based on said real address.

A method for performing a memory access defining an address at an earlier stage, in an arrangement having an instruction register, a general-purpose register, an address adder, and a translation look aside buffer, said method comprising the steps of:

• holding an inputted instruction in said instruction register, supplying a selection signal and outputting a content of the general-purpose register whose identifier is not zero, and outputting an all-zero output signal instead of said content of said general-purpose register whose identifier is equal to zero when either a base register identifier used to identify said general-purpose register or an index register identifier used to identify said general-purpose register, which are contained in said instruction, is zero;
• generating and holding a logical address having a page address and a page offset in said address adder, based upon the output supplied from said outputting step and said displacement bits derived in accordance with the contents indicated by said base register identifier and said index register identifier;
• selecting any one of a content of a base register, a content of an index register, and said page address supplied from said generating step in response to said selection signal;
• and
• receiving an output of said selecting step to access a real address corresponding to said output from a predetermined relation, and executing a memory access.

An information processing apparatus comprising:

• an instruction register for receiving a base register identifier, an index register identifier, and displacement bits;
• general-purpose registers, connected to said instruction register with each general-purpose register being selectively useable as a base register and an index register as designated by said base register identifier and said index register identifier;
• a logical address adder connected to said general purpose registers for generating a logical address having a page address portion and a page offset portion based on a content of a base register and displacement bits designated by an instruction received by said instruction register;
• a logical address register for storing the logical address generated by said logical address adder;
• a translation look-aside buffer for selecting a real address corresponding to the logical address;
• a real address register for storing said real address obtained by said translation look-aside buffer;
• and
• a first selecting unit for selecting one of a page address of said base register, a page address of said index register, and a page address of said logical address register, whereby said translation look-aside buffer selects a real address in accordance with a selection result of said first selecting unit.