Expedited execution of pipelined command having self-ordering operand processing requirements

In a pipelined computer having an E-unit for receiving a stream of executable code delivered thereto and processing the same at a code-dependent rate, and an I-unit for fetching and delivering code to the E-unit, a method for processing code which is prematurely output by the I-unit before the E-unit is instructed to process that code, the method comprising the steps of:

• (a) providing a side-track pipe coupled to receive code output by the I-unit output, said side-track pipe being in addition to a main-flow pipe that delivers code fetched by the I-unit to the E-unit;
• (b) temporarily storing I-unit outflow data which the E-unit has not yet been instructed to process in the side-track pipe;
• and
• (c) at a later time, delivering the temporarily stored data of the side-track pipe to the E-unit for immediate processing therein.

In a pipelined computer having an I-unit for supplying a stream of immediately executable code to an E-unit in accordance a first flow sequence although at times the E-unit requires the code to arrive in accordance with a different second flow sequence, a structure for delaying delivery to the E-unit of code prematurely processed by the I-unit before the E-unit is prepared to process said premature code, the structure comprising:

• (a) sidetrack pipe means provided at a juncture where I-unit outflow data flows toward an E-unit inlet or downstream of said juncture, the sidetrack pipe means being provided for storing data;
• (b) diverting means for diverting premature I-unit outflow data, which the E-unit is not yet prepared to process, to the sidetrack pipe means;
• and
• (c) switch means for delivering the stored data of the sidetrack pipe means to the E-unit in time-alignment with corresponding microinstructions.

A pipelined system having an upstream end and a downstream end, the pipelined system comprising:

• (a) first memory means for storing instructions, at least one of the instructions having plural operand specifiers that specify operand data further stored in the first memory means;
• (b) D-stage means, coupled to the first memory means, for receiving instruction signals from the first memory means and decoding the received instruction signals into one or more microinstruction specifying signals and one or more operand specifying signals;
• (c) specifier translating means, coupled to the D-stage means, for converting each operand specifying signal into an operand-specifying physical address signal;
• (d) B-stage means including a second memory means for storing a cache copy of operand data corresponding to the operand data of the first memory means, said B-stage means being coupled to receive the operand-specifying physical address signals output by the specifier translating means and to output correspondingly addressed ones of the cache copy operand data stored in the second memory means;
• (e) first X-stage means, coupled to receive the output ones of the cache copy operand data and to further receive execution flow control instructions, for performing first data processing operations in accordance with the execution flow control instructions and the received ones of the cache copy operand data and for outputting an outflow of data items derived from said first data processing operations;
• (f) data selecting/combining means having a first input for receiving the outflow of data items from the first X-stage means, a second input for receiving a flow of side-tracked data items, and an output, the data selecting/combining means being for selectively outputting in accordance with a supplied first control signal, either one of the data item outflows at its respective first and second inputs or a parallel combination derived from both outflows;
• (g) sidetrack pipe means having a copy-making input for making and storing copies of the data items outflowing from the first X-stage means and an output for outputting the copied and stored data items, said output of the sidetrack pipe means being coupled to the second input of the data selecting/combining means;
• and
• (h) second X-stage means, coupled to receive the output of the data selecting/combining means and to further receive the execution flow control instructions, for performing second data processing operations in accordance with the execution flow control instructions and the received output of the data selecting/combining means and for outputting an outflow of result data and plural control signals derived from said second data processing operations, said plural control signals including the first control signal supplied to the data selecting/combining means.