MIL-STD-1553 interface device having autonomous operation in all modes
AssigneeUnited Technologies Corporation
InventorsJeff P. Ziegler, John W. Pressprich, Anthony F. Jordan, Timothy D. Hornback, Gregory S. Carr
Life of this patent
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Abstract
An integrated circuit ("IC") implementing the three MIL-STD-1553 defined functions of bus controller, remote terminal, and monitor terminal implements a register-based architecture that allows for autonomous operation in all three modes, one or more modes being operable simultaneously, operation of the IC being autonomous in that the IC initializes operating variables in its internal registers and in external memory upon power up.
Claims15
An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and operates in one of several system selectable MIL-STD-1553 operating modes, said operating modes including 1) a bus controller mode, 2) a remote terminal mode, 3) a monitor mode and 4) concurrent monitor and remote terminal modes, said integrated circuit comprising:
- nonvolatile memory containing integrated circuit initialization data;
- means for receiving the mode signal indicative of the desired MIL-STD-1553 operating mode;
- means for selecting an operating mode from said several MIL-STD-1553 operating modes in response to the mode signal received by said means for receiving;
- means for detecting the system reset signal and for providing a reset signal which is active when the system reset signal is detected;
- and
- a microprocessor comprising;
- means for autonomously reading said initialization data when said reset signal is active;
- and
- means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations indicative of the operating mode said integrated circuit is commanded to operate in as defined by said mode signal.
An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and operates in one of several system selectable MIL-STD-1553 operating modes, said operating modes including 1) a bus controller mode, 2) a remote terminal mode, 3) a monitor mode and 4) concurrent monitor and remote terminal modes, said integrated circuit comprising:
- nonvolatile memory containing integrated circuit initialization data;
- a plurality of registers;
- means for receiving the mode signal indicative of the desired MIL-STD-1553 operating mode;
- means for selecting an operating mode from said MIL-STD-1553 operating modes in response to the mode signal received by said means for receiving;
- means for detecting the system reset signal and for providing a reset signal which is active when the system reset signal is detected;
- and
- a microprocessor comprising:
- means for reading said initialization data when said reset signal is active without the intervention of the host computer and for loading said initialization data into said plurality of registers and said volatile memory in response to said system reset signal;
- and
- means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations indicative of the operating mode said integrated circuit is commanded to operate in as defined by said mode signal.
An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and autonomously operates in one of several system selectable MIL-STD-1553 operating modes, said several system selectable MIL-STD-1553 operating modes comprising:
- (1) a bus controller mode;
- (2) a remote terminal mode;
- (3) a monitor mode;
- and
- (4) concurrent monitor and remote terminal modes, said integrated circuit comprising:
- nonvolatile memory containing integrated circuit initialization data;
- a selector, responsive to the mode signal, for selecting an operating mode from said several MIL-STD-1553 operating modes, the mode signal indicative of the MIL-STD-1553 operating mode to be selected;
- a detector for detecting the system reset signal and for providing a reset signal in response to the system reset signal;
- and
- a microprocessor comprising:
- means for autonomously accessing said initialization data in response to said reset signal;
- and
- means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations according to an operating mode selected from said several MIL-STD-1553 operating modes by said selector for selecting an operating mode in response to the mode signal.
A method for interfacing a system with a MIL-STD-1553 data bus on an integrated circuit, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and autonomously operates in one of several system selectable MIL-STD-1553 operating modes, said several system selectable MIL-STD-1553 operating modes comprising:
- (1) a bus controller mode;
- (2) a remote terminal mode;
- (3) a monitor mode;
- and
- (4) concurrent monitor and remote terminal modes, said method comprising:
- storing initialization data of an integrated circuit in nonvolatile memory;
- selecting an operating mode from said several MIL-STD-1553 operating modes in response to the mode signal, the mode signal being indicative of the MIL-STD-1553 operating mode to be selected;
- detecting the system reset signal and generating a reset signal in response to said detected system reset signal;
- and
- autonomously accessing said stored initialization data by means of a microprocessor in response to said reset signal;
- and
- executing, in response to the reset signal, a predetermined sequence of signal processing operations according to an operating mode selected from said several MIL-STD-1553 operating modes by said means for selecting an operating mode in response to the mode signal, said executing being performed by said microprocessor.
Dependencies are inferred from the claim text.