US 5,490,253 AGranted

Multiprocessor system using odd/even data buses with a timeshared address bus

AssigneeAT&T Corp.

InventorsSubhasis Laha, Dennis J. Thompson

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Abstract

Bus arrangements are disclosed for interconnecting processors and main memory modules of a shared memory multiprocessor system. A single address bus interconnects all processors and memory modules, but odd and even memory modules communicate data to and from the processors via an odd and an even data bus. Each reading of memory occupies four bus cycles on one of the data buses. On the address bus, two of each of the four cycles are available for addressing odd and even memory modules, and the other two are available for sending invalidation addresses to the caches of the processors. The single address bus is used for transmitting a relatively narrow (32-bit) address word throughout the system, one address on each bus cycle, while the data buses are time shared to transmit a wide data word (256-bit) in four bus cycles, and each data bus is only connected to half of the main memory modules. Such an arrangement makes efficient use of limited bus resources to transmit information when and where it is needed.

Claims18

Dependent claims

In a multiprocessor system comprising:

a plurality of processor means for processing data;
a plurality of main memory modules;
and
bus means for interconnecting said processors and said memory modules;
the bus means of the invention comprising:
a single time-shared address bus, for transmitting a plurality of addresses in a plurality of time intervals said addresses identifying data to be accessed in said main memory modules, connected to all of said processor means and all of said memory modules;
and
first and second data buses, each of said first and second data buses connected to all of said processor means, each of said memory modules connected to only one of said first data bus or said second data bus;
a snoop bus connected to each of said processor means for conveying signals to each of said processor means indicating that one processor of said processor means has detected a match between an address on said address bus and an address of data stored in a cache memory means of said one processor;
wherein each of said memory modules stores data for a contiguous block of addresses, wherein at least one first memory module, connected to the first data bus, and at least one second memory module, connected to the second data bus, receive different addresses during different interleaved sets of time slots from said time-shared address bus, said different interleaved sets of time slots dedicated to each of said memory modules connected to said first and said second data buses, and wherein the memory modules connected to each of the first and second data buses transmit responses at variable time slots with data stored at one of said addresses over said first and said second data buses, respectively, with at least one of the time slots of the responses being transmitted simultaneously.

7 more elements

A multiprocessor system comprising:

a first plurality of processor means for processing data;
a second plurality of main memory modules;
and
bus means for interconnecting said processor means and said memory modules;
the bus means of the invention comprising:
a single time multiplexed address bus for transmitting one address during each time slot of the address bus connected to all of said processor means and all of said memory modules, said address identifying data in said main memory modules;
and
first and second data buses, each of said first and second data buses connected to all of said processor means and each of said memory modules connected to only one of said first and second data buses;
wherein each of said memory modules stores data for a contiguous block of addresses, wherein at least one first memory module, connected to the first data bus, and at least one second memory module, connected to the second data bus, receive different addresses during different interleaved sets of time slots from said address bus, said different interleaved sets of time slots dedicated to each of said memory modules connected to said first and said second data buses, and wherein the memory modules connected to each of the first and second data buses transmit responses at different time slots with data stored at one of said addresses over said first and said second data buses, respectively, with at least one of the time slots of the responses being transmitted simultaneously;
wherein each of said processor means comprises cache memory means, for storing data and corresponding addresses and for storing a state of the data for each corresponding address, one of the states being an invalid state wherein addresses on said address bus are transmitted to said processors for checking against said corresponding addresses of data stored in each said processor cache memory means;
wherein said address bus conveys invalidation addresses for invalidating data for said invalidation addresses stored in cache memory means of said processors among said processor means, and said address bus can transmit one address during a time slot, and wherein said address bus transmits addresses to said memory modules during a first half of the time slots, and said address bus conveys said invalidation addresses during a second half of said time slots;
a snoop bus connected to each of said processor means for conveying signals with data characterizing a state of data for a corresponding address of data stored in cache means of one of said processor means, indicating that said one processor has detected a match between an address on said address bus and an address of data stored in cache memory means of said one of said processors;
wherein for one of said states, said one processor means provides data from its cache memory means to one of said first or second data buses and to one of said memory modules;
wherein said address bus conveys to said plurality of processor means and to said plurality of main memory modules a plurality of addresses for each data transfer cycle from one of said memory modules, said data transfer cycle corresponding to a transmission of data for one of said plurality of time multiplexed addresses;
wherein access to said address bus is allocated by arbitration means, comprising a global arbiter and a plurality of distributed arbiters, wherein all processors which request access to said address bus are granted access for a first request before any processor is granted access for a second request;
wherein one of said processor means comprises a peripheral memory controller for controlling a peripheral memory and wherein said one of said processor means transmits invalidation signals when main memory is updated from said peripheral memory.

13 more elements

Dependencies are inferred from the claim text.