Phase-locked loop circuit having ring oscillator

Abstract

A phase-locked loop circuit has a ring oscillator comprising a plurality of 1st, 2nd, . . . , nth inverter chains composed of series-connected 21, 22, . . . , 2n inverters (n.gtoreq.2), respectively, an (n+1)th inverter chain composed of an odd number of series-connected inverters, and a plurality of 1st-nth selectors associated with the 1st-nth inverter chains, respectively, for selectively outputting input signals to and output signals from the 1st-nth inverter chains, the 1st-nth inverter chains being combined respectively with the 1st-nth selectors in respective combinations, the combinations and the (n+1)th inverter chain being connected in a ring configuration. A phase comparator compares an input clock signal and an oscillated clock signal from the ring oscillator in phase, and applies an output signal to a control circuit which controls the 1st-nth selectors to synchronize the oscillated clock signal with the input clock signal.

Dependencies are inferred from the claim text.