Digital data receiver

Abstract

An apparatus for restoring a symbol timing of a signal received at a receiving side of a digital communication system. The invention includes a first sampling section which is applied with a received signal, for sampling in accordance with a first frequency higher than the sampling frequency possessed by the received signal; a second sampling section which is applied with an output signal of the first sampling section, for sampling in accordance with a first clock signal applied from a symbol timing restoring circuit; an equalizer which is applied with the output signal of the second sampling section for equalizing; a third sampling section which is applied with the output signal of the equalizer, for sampling in accordance with a second clock signal applied from the symbol timing restoring circuit; and a symbol timing restoring circuit which is applied with the output signal of the second sampling section for detecting a present sampling position and generating the first clock signal and the second clock signal variably changed with the sampling position based on the detected present sampling position and an optimum sampling position. Accordingly, a tracing of an optimum sampling position is possible, and further a sampling position tracing even with respect to the position between samples is possible, so that more exact restoration of the symbol data is possible.

Dependencies are inferred from the claim text.