Error correction system for n bits using error correcting code designed for fewer than n bits

A computer memory interface between a memory array storing data words n bits wide and m check bits utilized with said data words, and a computer bus n data bits wide, comprising:

• a memory bus having n bits connected to the n data bits and m bits connected to the m check bits of the memory array;
• a plurality of check bit generator circuits, each check bit generator circuit providing less than n data bits and m check bits based on the data bits provided by that check bit generator circuit to said memory bus and receiving less than n data bits from the computer bus, wherein the sum of the number of data bits provided to the memory bus by all of said check bit generator circuits equals n, the sum of the number of check bits provided to the memory bus by all of said check bit generator circuits equals m, and the sum of the number of data bits received by all of the check bit generator circuits equals n;
• a plurality of error detection circuits, each error detection circuit receiving less than n data bits and less than m check bits from said memory bus and providing less than n data bits to the computer bus, wherein the sum of the number of data bits received from the memory bus by all of said error detection circuits equals n, the sum of the number of check bits received from the memory bus by all of said error detection circuits equals m, and the sum of the number of data bits provided to the computer bus by all of said error detection circuits equals n, and wherein each said error detection circuit detects single-bit errors, two-adjacent-bits errors and other errors;
• and
• a plurality of error correction circuits connected between said error detection circuits and the computer bus, each said error correction circuit providing less than n data bits to the computer bus and receiving less than n data bits from one of said error detection circuits, wherein the sum of the number of data bits received from all of the error detection circuits by all of the error correction circuits equals n, and the sum of the number of data bits provided to the computer bus by all of said error correction circuits equals n, and wherein each said error correction circuit corrects single-bit and two-adjacent-bits errors detected by each said error detection circuit and provides corrected data to the computer bus.