A circuit arrangement for decoding RS-coded data signals coded in accordance with a code generator polynomial G(x)=(x+.alpha..sup.0+b)(x+.alpha..sup.1+b) . . . (x+.alpha..sup.15+b), where b=0 or 120, comprising:
- (a) a first device for forming syndromes (S(x)) for successive data blocks and for determining erasure locations (L(x)) in the RS-coded data signals,
- (b) a second device connected to the first device for using a Euclid's algorithm in which
- T.sub.s (x)=(Q.sub.s-1 (x)T.sub.s-1 (x)+T.sub.s-2 (x)
- R.sub.s (x)=(Q.sub.s-1 (x))R.sub.s-1 (x)+R.sub.s-2 (x) and Q.sub.s-1 (x)=(R.sub.s-2 (x)/R.sub.s-1 (x), in which T.sub.s (x) is an error location polynomial, R.sub.s (x) is an error value polynomial, and Q.sub.s-1 (x) is an intermediate value polynomial,
- (c) a third device connected to the second device for determining error locations X.sub.k and error values Y.sub.k by means of a Chien zero search defined by the relation:
- ##EQU8## in which b is the constant offset in exponents of .alpha. in the code generator polynomial and T'(X.sub.k) is the first derivative at location X.sub.k,
- (d) a fourth device connected to the third device for correcting data words within an RS-coded data block on the basis of the determined error locations X.sub.k and error values Y.sub.k,
- (e) said first device comprising syndrome generators for determining syndromes (S(x)), each generator comprising
- (i) first exclusive-OR stages to whose inputs data words of the RS-coded data signals are bit-parallel applied,
- (ii) a first register for storing the data words supplied by the first exclusive-OR stages,
- (iii) a first multiplier for multiplying the data words present at the output of the first register by a constant .alpha..sup.i, in which i is a control variable from 0 to 15,
- (iv) a second multiplier for multiplying the data words present at the output of the first register by a constant a.sup.i+120,
- (v) a first multiplexer which passes on the data from an output of the first multiplier to other inputs of the first exclusive-OR stages when RS-coded data signals in accordance with a code generator polynomial starting with .alpha..sup.0 are decoded and which passes on the data from an output of the second multiplier to the other inputs of the exclusive-OR stages when RS-coded data signals in accordance with a code generator polynomial starting with .alpha..sup.120 are decoded,
- (f) said third device comprising:
- (i) an up-counter for up-counting the data words present in a data block and for supplying a counting value (x) for the Chien zero search,
- (ii) a first stack memory in which the counting values (x) supplied by the up-counter can be written,
- (iii) a second stack memory in which data read from the first stack memory can be written at the end of each data block,
- (iv) a third stack memory in which the error values (Y.sub.k) can be written simultaneously when the counting values (X.sub.k) are written in the first stack memory,
- (v) a fourth stack memory in which data read from the third stack memory can be written at the end of a data block, and
- (vi) an inverse counter operated parallel to the up-counter and having an offset of .alpha..sup.-120 with respect to the up-counter,
- (g) said fourth device comprising:
- (i) a down-counter for down-counting, starting with the value of a data block length,
- (ii) an arrangement for comparing the counting value present at an upper position in the second stack memory with the counting values supplied by the down-counter for deriving a control signal (Found) when the values provided are equal,
- (iii) an AND gate, one input of which is connected to an output of the comparison arrangement,
- (iv) a further second up-counter controlled by the inverse counter and having an offset of 120,
- (v) a third multiplier for multiplying the error value (X.sub.k) present at an upper position in the fourth stack memory by the counting value supplied by the further second up-counter,
- (vi) a second multiplexer which passes on the error value (X.sub.k) present at an upper position in the fourth stack memory to another input of the AND gate when RS-coded data signals in accordance with a code generator polynomial starting with .alpha..sup.0 are decoded and which passes on the value Y.sub.k present at the output of the second multiplier to the other input of the AND gate when RS-coded data signals in accordance with a code generator polynomial starting with .alpha..sup.120 are decoded,
- (vii) second exclusive-OR stages whose first inputs receive the signal which can be derived from outputs of the AND gate, whose second inputs receive bit-parallel signal delay-adapted data words of the RS-coded data signals and from whose output error-corrected data words can be derived.