Boundary scan cell

A Boundary-Scan cell interposed between an internal logic block of an electronic device and a node of that device, the cell being adapted for serial connection with each of a plurality of Boundary-Scan cells in a single chain for facilitating Boundary-Scan testing during a first interval, comprising:

• a shift flip-flop for latching an input bit and generating an output bit in accordance with the latched input bit;
• a shift multiplexer having a first input which receives an input bit and a second input which receives a second input bit, the shift multiplexer passing the input bit at a separate one of its first and second inputs to the shift flip-flop in response to an external control bit applied to the multiplexer;
• an update flip-flop coupled to the shift flip-flop for latching the bit previously loaded into the shift flip-flop;
• a system flip-flop having asynchronous preset and clear capability, the flip-flop having a D input and Q output each coupled to a separate one of the internal logic block of the device and the device node, respectively,
• a logic circuit coupled to system flip-flop and responsive to both the bit latched in the update flip-flop and to an external MODE bit for forcing the system flip-flop during the first interval to provide a bit at its Q output which corresponds to the bit latched in the update flip-flop and for allowing the system flop-flop to pass a bit appearing at its D input to its Q output during an interval other than during the first interval;
• and
• the shift multiplexer being supplied at its first input supplied with an input bit corresponding to the bit appearing at the Q output of the system flip-flop.