US 5,490,115 A · Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation

Abstract

A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.

Claims28

Dependent claims

A memory system for writing a background pattern to a plurality of memory cells, said memory system comprising:

a two-dimensional array having said plurality of said memory cells arranged in M rows and N columns;
each of said rows coupled to a corresponding word line, each of said columns coupled to a corresponding first bit line;
a word line control circuitry for controlling said word lines, said word line control circuitry coupled to said word lines;
a gang write circuitry having a plurality of driver circuits, said plurality of driver circuits comprising a plurality of inverter sets, said gang write circuitry coupled to said two-dimensional array.

1 more element

A memory system for writing a background pattern to a plurality of memory cells, said memory system comprising:

a two-dimensional array having said plurality of said memory cells arranged in M rows and N columns;
each of said rows coupled to a corresponding word line, each of said columns coupled to a corresponding first bit line;
a word line control circuitry for controlling said word lines, said word line control circuitry coupled to said word lines;
a gang write circuitry having a plurality of driver circuits, said gang write circuitry coupled to said two-dimensional array, wherein said driver circuits comprise a plurality of inverter sets and each of said plurality of inverter sets having a corresponding first inverter, each of said first inverters having a corresponding first output and a corresponding first input;
each of said first outputs coupled to a corresponding one of said first bit lines, each of said first inputs coupled to a corresponding first test signals and further comprising:
each of said columns coupled to a corresponding second bit line;
each of said plurality of inverter sets further including a corresponding second inverter, each of said second inverters having a corresponding second output and a corresponding second input;
each of said second output coupled to a corresponding one of said second bit lines, each of said second inputs coupled to a corresponding second test signal;
wherein said gang write circuitry is inactive during a non-test read and write operation.

6 more elements

Dependencies are inferred from the claim text.

Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation

Life of this patent

Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation

Life of this patent

Abstract

Claims28