Multi-port memory device with multiple sets of columns
AssigneeMicron Technology, Inc.
InventorsGlen E. Hush, Stephen L. Casper
Life of this patent
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Abstract
A multi-port memory device includes a row-column array, a random access port, a plurality of bidirectional serial access memory (SAM) ports, and a switching network for coupling SAM ports to sets of columns. A column is defined as a number of memory cells sharing a sense amplifier. Sets of columns are defined in one rectangular region or among several rectangular regions of the array. The switching network selectively couples each SAM port with each set, each set with each other set, and each SAM port with each other SAM port. A video random access memory (VRAM) or a multi-port dynamic random access memory (DRAM) of the present invention provides increased flexibility in smaller die area.
Claims8
A multi-port memory comprising:
- a. a dynamic random access memory array, the array comprising a first, a second, and a third set of columns each column comprising a sense amplifier, the first set comprising a predetermined number of columns, the second and the third set comprising the predetermined number of columns;
- b. a random access circuit coupled to the array, the random access circuit comprising a column decoder for concurrently enabling a sense amplifier from each set;
- c. a first, a second, and a third serial access circuit coupled to the array, the first, the second, and the third serial access circuit respectively comprising a first, a second, and a third plurality of serial access memory cells and a first, a second, and a third pointer decoder for enabling serial access of a serial access memory cell of the respective plurality;
- and
- d. a switching circuit comprising a plurality of buses equal in number to the predetermined number, a plurality of first transfer gates for coupling the enabled sense amplifiers to a selected bus of the plurality of buses, and a plurality of second transfer gates for coupling the selected bus to the enabled serial access memory cells.
Dependencies are inferred from the claim text.