High speed current mirror memory cell architecture

Abstract

A memory cell (i.e. CMMC) for use in GaAs circuits such as MESFETs wherein read and write operations can both be performed using as few as two access transistors biased as current mirrors to driver transistors of the cell. This new memory cell offers larger read access currents for faster access times and also faster write times than in a conventional memory cell. This cell does not require that the driver transistors be scaled with respect to the access transistors, resulting in a smaller cell area. In the CMMC, the gate of each access transistor is biased by a storage node voltage. The source node of each access transistor is biased by a word line which is pulled low, towards ground. As a result, each access transistor has a gate-source voltage of V.sub.GS (access)=V.sub.CS +V.sub.CG -V.sub.WORD where V.sub.CS is the cell storage voltage (with respect to cell ground), V.sub.CG is the cell ground voltage and V.sub.WORD is the word line voltage at the cell. By varying the cell ground voltage, the memory cell can be biased for read or write operations. By adjusting both the cell ground and word line voltages, additional control can be gained over the read access current and access time.

Dependencies are inferred from the claim text.