US 5,490,101 A · Digital data multiplying circuit

Abstract

A digital data multiplying circuit has a double clock alternating sampler for alternately sampling the digital data applied from a plurality of input buses by a time-division system in accordance with a first system clock, a dual coefficient alternating multiplier for alternately multiplying digital data of each bus sampled by the double clock alternate sample with the multiplying coefficient corresponding to the digital data according to a first system clock and first and second primary clocks, and a data restorer for dividing the synchronized product data of the dual coefficient alternating multiplier into input data units according to the first system clock, a second system clock and the second primary clock and for outputting the result on a plurality of output buses. As a result, the digital data input to a plurality of input buses can be multiplied by a single multiplier.

Claims14

Dependent claims

A digital data multiplying circuit for multiplying n-bit digital data applied to a plurality of digital data input buses with a respective plurality of coefficients applied to a plurality of coefficient input buses, and for outputting the products thereof, said digital data multiplying circuit comprising:

double clock alternating sampler means for performing alternate sampling, according to a first system clock, on digital data applied from said plurality of digital data input buses, and for outputting said alternately sampled digital data as alternately sampled digital data;
dual coefficient alternating multiplier means for alternately multiplying said alternately sampled digital data output by said double clock alternating sampler means with said respective plurality of coefficients, according to said first system clock, a first primary clock, and a second primary clock, and for outputting said alternately multiplied alternately sampled digital data as product data;
and
data restorer means for dividing said product data output by said dual coefficient alternating multiplier means into respective multiplied digital data outputs according to said first system clock, a second system clock, and said second primary clock, and for outputting said respective multiplied digital data onto a plurality of output buses.

1 more element

a double clock alternating sampler which alternately samples digital data applied from said plurality of digital data input buses according to a first system clock, and which outputs said alternately sampled digital data as alternately sampled digital data;
a dual coefficient alternating multiplier which alternately multiplies said alternately sampled digital data output by said double clock alternating sampler with said respective plurality of coefficients, according to said first system clock, a first primary clock, and a second primary clock, and which outputs said alternately multiplied alternately sampled digital data as product data;
and
a data restorer which divides said product data output by said dual coefficient alternating multiplier into respective multiplied digital data outputs according to said first system clock, a second system clock, and said second primary clock, and which outputs said respective multiplied digital data onto a plurality of output buses.

1 more element

Dependencies are inferred from the claim text.

Digital data multiplying circuit

Life of this patent

Digital data multiplying circuit

Life of this patent

Abstract

Claims14