Method of extracting parameters for circuit simulation

In a method of circuit simulation for an integrated circuit device having a plurality of field-effect transistors, a parameter extraction method comprising the steps of:

• (a) preparing layout data representing a layout pattern of one of said plurality of field effect transistors;
• (b) adding an index symbol data to said layout data when said layout pattern is a non-linear pattern, thereby forming designed pattern data;
• (c) extracting a circuit parameter of said one of said plurality of field effect transistors based upon the layout data and the designed pattern data;
• (d) repeating steps (a)-(c) for each of said plurality of field effect transistors;
• wherein said non-linear pattern is a bent gate pattern having source and drain regions defined on opposite sides thereof;
• wherein said circuit parameter is an effective channel width of said field effect transistor;
• and
• wherein said bent gate pattern has a serpentine structure having (N.sub.f +N.sub.r .gtoreq.1) bends where N.sub.f assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said drain region and N.sub.r assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said source region, and
• said effective channel width W.sub.eff is determined as
• W.sub.eff =.SIGMA.W.sub.1 -{N.sub.f (1-K.sub.f)+N.sub.r (1-K.sub.r)}L.sub.eff
• Where, .SIGMA.W.sub.1, K.sub.f, K.sub.r and L.sub.eff represent the following:
• .SIGMA.W.sub.1 :
• a total length of the bent gate pattern as measured along its central lines,
• K.sub.f, K.sub.r :
• current control capability coefficients of the bends for N.sub.f and N.sub.r, respectively, and
• L.sub.eff :
• an effective channel length of the bent gate pattern determined in consideration of unintentional influence of formation of source/drain regions on a channel length.