Constant delay interconnect for coupling configurable logic blocks
AssigneeAdvanced Micro Devices, Inc.
InventorsOm P. Agrawal, Michael J. Wright, Ju Shen
Life of this patent
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Abstract
A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. The interconnect network has longlines and programmable interconnect points (PIP's). PIP's are symmetrical distributed in a partially populated fashion within the interconnect network such that a substantially same signal propagation delay develops for each signal routed along a program-selected longline from a CLB adjacent to that longline to an IOB adjacent to that longline.
Claims20
A programmable integrated circuit comprising:
- (a) a plurality of programmably configurable logic blocks for carrying out program-defined logic functions, each of said configurable logic blocks having longline input means for inputting signals to the respective configurable logic block, and general output means for outputting signals from the respective logic block;
- and
- (b) a programmably configurable interconnect network for providing program-defined routing of signals between the plurality of programmably configurable logic blocks,
- wherein said configurable interconnect network includes:
- (b.1) a first group of at least four longlines, said first group of longlines extending by a first subset of at least four of the configurable logic blocks;
- and
- (b.2) a first symmetrical distribution of programmable interconnect means provided along the first group of longlines for providing program-defined coupling between respective combinations of more than one but not all of the first group of longlines and corresponding combinations of more than one but not all of the first subset of configurable logic blocks, the first symmetrical distribution of the programmable interconnect means being such that a substantially same signal propagation delay develops for each longline in said first group when intercoupling a corresponding one or more of the first subset of configurable logic blocks.
A programmable integrated circuit comprising:
- (a) a plurality of programmably configurable logic blocks for carrying out program-defined logic functions;
- (b) a plurality of input/output blocks for providing an interface between the plurality of configurable logic blocks and points outside said integrated circuit, each of said input/output blocks having input means for inputting signals to the plurality of programmably configurable logic blocks, and output means for outputting signals from the plurality of programmably configurable logic blocks;
- and
- (c) a programmably configurable interconnect network for providing program-defined routing of signals between the plurality of programmably configurable logic blocks and the plurality of input/output blocks,
- wherein said configurable interconnect network includes:
- (c.1) a first group of at least four longlines, said first group of longlines extending by a first subset of at least four of the configurable logic blocks and extending to, and coupling to a corresponding first subset of at least two of the input/output blocks;
- and
- (c.2) a first symmetrical distribution of programmable interconnect means provided along the first group of longlines for providing program-defined coupling between respective combinations of more than one but not all of the first group of longlines and corresponding combinations of more than one but not all of the first subset of configurable logic blocks, the first symmetrical distribution of the programmable interconnect means being such that a substantially same signal propagation delay develops for each longline in said first group when coupling a corresponding one or more of the first subset of configurable logic blocks to a corresponding one or more of the first subset of input/output blocks.
Dependencies are inferred from the claim text.