Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch

Abstract

A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to a FIFO concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the FIFO, the memory control logic waits to detect a tag indicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the FIFO to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.

Dependencies are inferred from the claim text.