Timing logic system and method for selectably controlling a high resolution charge coupled device image sensor of the type having two line pixel registers to provide a high resolution mode and alternatively a television resolution mode of picture imaging

A timing logic system for generating standard synchronizing (sync) and control signals in accordance with a television standard and for generating horizontal and vertical control signals required by a high resolution charge coupled device (CCD) image sensor of the type providing horizontal lines of pixel image signals of vertical image frames from two line pixel registers for alternative modes of operation, the timing logic system comprising:

• a frequency generator adapted to provide signals referenced to a standard television frequency sub-carrier (fsc);
• a television-standard timing generator adapted to be driven by a signal from the frequency generator and adapted to provide the standard sync and control signals in accordance with the television standard;
• a plurality of timers adapted to generate signals having respective durations and being precisely referenced to each other and to ones of the standard sync and control signals;
• a pixel clock generator adapted to generate a pixel clock, the pixel clock generator being adapted to be driven by a signal from the frequency generator;
• and
• a plurality of logic units adapted to generate horizontal, horizontal line pixel register shift, vertical, and vertical frame shift CCD control signals and display field control signals from a logical combination of respective ones of the pixel clock, timer signals, and the standard sync and control signals;
• thereby controlling selected ones of the timers and the logic units to provide for a high resolution mode of operation of the CCD image sensor in which consecutive single horizontal lines of pixel image signals are outputted at the same time from each one of the two line pixel registers for each vertical image frame of a picture to a high resolution picture unit and to provide for a television resolution mode of operation of the CCD image sensor in which alternate pairs of consecutive horizontal lines of pixel image signals are outputted from a first one of the two line pixel registers for a first vertical image frame of the picture through a switch means controlled by a first one of the display field control signals to form a first display field of a standard television display, and are outputted from a second one of the two line pixel registers for a consecutive second vertical image frame of the picture through the switch means controlled by a second one of the display field control signals to form a second display field interlaced with the first display field of the television display.

A method for controlling a high resolution CCD image sensor of the type having at least a pair of two line pixel registers and having a large number of horizontal lines of pixel image signals per image frame to obtain in a television resolution mode of operation a reduced number of lines of video signals synchronized in interlaced first and second display fields for display in accordance with a television standard and alternatively to obtain all of the lines of pixel image signals from the CCD image sensor outputted from the line pixel registers for utilization by a high resolution picture unit, the method comprising the steps of:

• generating standard sync and control signals as required by a standard television display;
• generating a pixel clock;
• generating a plurality of timed pulses referenced to the standard sync and control signals;
• generating three horizontal CCD control signals from a logical combination of the pixel clock and ones of the timed pulses;
• generating vertical CCD control signals having a selectable number of vertical shift pulses from a logical combination of ones of the timed pulses;
• generating line pixel register shift control signal pulses having a selectable temporal relationship to the vertical shift pulses from a logical combination of ones of the vertical shift pulses and the pixel clock;
• generating vertical CCD control signals having a fixed number of frame shift pulses from a logical combination of ones of the timed pulses and the standard sync and control signals;
• generating display field control signals for displaying of selected numbers of alternate pairs of consecutive horizontal lines of pixel image signals outputted from a first one of the two line pixel registers for a first vertical image frame of a picture through a switch means controlled by a first one of the display field control signals to form a first display field of the standard television display, and outputted from a second one of the two line pixel registers for a consecutive second vertical image frame of the picture through the switch means controlled by a second one of the display field control signals to form a second display field interlaced with the first display field of the television display, the display field control signals generated from a logical combination of ones of the standard sync and control signals and the timed pulses;
• and
• selecting the numbers of the vertical shift pulses and the temporal relationship thereto of the line pixel register shift control signal pulses in accordance with a high resolution mode of outputting single horizontal lines of pixel image signals from each one of the two line pixel registers of the CCD image sensor and alternatively selecting the numbers of the vertical shift pulses, the temporal relationship thereto of the line pixel register shift control signal pulses and the display field control signals in accordance with the television resolution mode of outputting the alternate pairs of consecutive lines of pixel image signals in the interlaced first and second display fields of the television standard.