US 5,489,902 A · Dynamic power saving video DAC

Abstract

Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance. At the end of sleep mode, the current source may be rapidly turned back on by turning on one of the MOSFETS. Performance of the video DAC is therefore not affected, while power dissipation is substantially reduced, facilitating higher-level integration and compliance with the Green PC standard. Reduced power dissipation also allows for use of an inexpensive chip package, reducing manufacturing cost, and increases reliability of the chip.

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Drawings

Claims12

Dependent claims

A digital to analog converter comprising

current source means for producing a current;
current steering means connected to the current source means, the current steering means comprising switching means responsive to first and second control signals, respectively, for steering the current into one of a load and a current return path;
and
means for generating the first and second signals each as a logical combination of a video data signal and a sleep signal, the sleep signal, when it is active, causing both the first and second switching means to turn off, the current source means remaining turned on;
whereby dynamic power management may be performed in which the first and second switching means are turned off for relatively short periods of time and afterwards turned quickly back on.

2 more elements

A power-saving video digital to analog converter having an active mode and a sleep mode, comprising:

a source of power and a source of ground;
a reference generator that produces a control signal;
a plurality of transistors connected to power and to the control signal in current mirror configuration so as to produce a plurality of substantially identical currents at a corresponding plurality of circuit nodes;
a corresponding plurality of transistor pairs, both transistors within each transistor pair being connected to a same one of the plurality of circuit nodes;
and
a corresponding plurality of signal pairs, each signal of a pair being connected to a transistor of a pair to turn that transistor on or off, the signals in each signal pair being such that, in active mode, one and only one transistor in each transistor pair is fully turned on at a time and such that, in sleep mode, both transistors in each transistor pair are fully turned off, said plurality of transistors connected to power and to the control signal in current mirror configuration remaining turned on;
whereby dynamic power management may be performed in which each transistor in each transistor pair is turned off for relatively short periods of time and afterwards turned quickly back on.

4 more elements

Dependencies are inferred from the claim text.

Description2,084 words

Summary1,632 words

#1. Field of the Invention

#The present invention relates to video digital to analog converters (video DACs) and more particularly to current steering video DAC in which the current is periodically turned off to reduce power dissipation.

#2. State of the Art

Brief description of the drawings2 figures

#The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:

#FIG. 1 is a circuit diagram showing in part a conventional power-saving

#digital to analog converter; and

Detailed description391 words

#Referring to FIG. 2, the dynamic power-down DAC of a preferred embodiment of the present invention has a similar circuit configuration as a conventional DAC without the power-down feature (i.e., without the switches S1 and S2 of FIG. 1). As compared to the conventional DAC without the power-down feature, however, the control signals for the pass transistor pairs of the present dynamic power-down DAC have an extra control signal SLEEP which is logically combined with the digital color data.

#During power-down operation, the current paths of the current sources (i.e., M1, M2 and M3) are turned off by shutting off all the pass transistor pairs (i.e., M11 and M12, M21 and M22, M31 and M32) at the same time when the control signal SLEEP becomes active during the blanking period. The gates of the pass transistor pairs are controlled by complementary digital video signals "logic ORed" with a SLEEP signal. During the power down period, both gates of the pass transistor pairs are forced to VDD to shut off the current paths and reduce power consumption.

#When the current sources are turned back on after the blanking signal goes inactive, they can "wake up" , or be turned fully on, within one or two pixel clock periods after the SLEEP signal goes low. The much faster response time of the present power-saving DAC (as compared to the power-saving DAC of FIG. 1) is made possible in that the parasitic capacitance of the gates of the pass transistor pairs (i.e., M11 and M12, M21 and M22, M31 and M32) is much smaller than that of the current sources (i.e. M1, M2 and M3).

Facts

Application

08/233,928Filed 28 Apr 1994

Granted

6 Feb 1996

Term ended

28 Apr 2014

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification3 codes

H03M 1/002
Analogue/digital conversion; Digital/analogue conversion: provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower…
H03M 1/742
Simultaneous conversion: using current sources as quantisation value generators
H03M
Coding

Dynamic power saving video DAC

Life of this patent

Dynamic power saving video DAC

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims12

Description2,084 words

Drawings

Classification3 codes

Life of this patent

Description2,084 words