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US 5,489,861 AGranted
High power, edge controlled output buffer
AssigneeNational Semiconductor Corporation
InventorMichael J. Seymour
Life of this patent
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AssigneeNational Semiconductor Corporation
InventorMichael J. Seymour
Estimating the term…
An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on. There is also a contingent bipolar pull-down transistor to aid in switching the buffer output from logic-high to logic-low if the MOS transistors and first bipolar transistor acting together are not sufficient. Later, as current-sinking is being turned off, there is again a sequential deactivation of the pull-down transistors so as to round the turn-off curve. The dual MOS/bipolar pull-down scheme provides a degree of temperature compensation of the pulldown current and a lower output capacitance than when one type of transister is used.
An output buffer circuit comprising a Darlington pair output pullup stage and a means for providing a staged voltage increase to an input base node of said Darlington pair, said staged voltage increase comprising a first, fast increase up to a first predetermined voltage level, followed by a second, slower increase up to a second predetermined voltage level, said means for providing a staffed voltage increase including at least one fixed capacitance means charged with a constant current, and said staged voltage increase means further including a means for delaying the charging of said fixed capacitance, said means for delaying the charging of said fixed capacitance comprising current-voltage characteristics similar to the base-emitter junctions of the transistors of said Darlington pair.
An output buffer circuit comprising a Darlington pair output pullup stage and a means for providing a staged voltage increase which includes a fixed capacitance charged with a constant current produced by a current mirror coupled between a high-potential power rail and a first base node of a first Darlington transistor of said Darlington pair output pullup stage, and a first diode connected between said first base node and a high side of a first charging capacitor of said fixed capacitance, wherein a low side of said first charging capacitor is coupled directly to a low-potential power rail.
An output buffer circuit comprising a controlled pullup circuit, wherein said controlled pullup circuit includes
An output buffer circuit comprising both a MOS transistor output pulldown stage and a bipolar transistor output pulldown stage, wherein said MOS transistor output pulldown stage and said bipolar transistor output pulldown stage are coupled to a buffer output node, said MOS transistor output pulldown stage comprising a first MOS pulldown transistor coupled between said buffer output node and a low-potential power rail, wherein a gate node of said first MOS pulldown transistor is coupled to a controlled-current source through a current switch activatable by a buffer input voltage applied to a buffer input node, said bipolar stage comprising a first bipolar pulldown transistor coupled between said buffer output node and said low-potential power rail and wherein a base node of said first bipolar pulldown transistor is coupled to a high-potential power rail through a first driver transistor, wherein a control node of said first driver transistor is coupled to said buffer input node, wherein a first delay cell is interposed between said control node of said first driver transistor and said buffer input node, wherein said MOS transistor output pulldown stage includes a second MOS pulldown transistor coupled in parallel with said first MOS pulldown transistor between said buffer output node and said low-potential power rail, wherein a gate node of said second MOS pulldown transistor is coupled to said controlled-current source through said current switch and also through a diode.
A method for gradually turning off current sinking in an output buffer, said method comprising using a plurality of pulldown transistors in parallel but controlled by separate control node discharge transistors, wherein said separate control node discharge transistors have a range of discharge rate capacities so as to effect turn on of each of said plurality of pulldown transistors at a different time.
A method of minimizing output capacitance in an output buffer for a given current-sinking capacity, said method comprising coupling a first transistor set in parallel with a second transistor set, said first transistor set comprising a first MOS pulldown transistor in parallel with a second MOS pulldown transistor, said second transistor set comprising a first bipolar pulldown transistor in parallel with a second bipolar pulldown transistor, and using a pulldown turn:on circuit to turn on said first MOS pulldown transistor then said second MOS pulldown transistor, followed by turning on said first bipolar pulldown transistor then said second bipolar pulldown transistor.
A method for producing in an output buffer a pulldown current sourcing waveform within predetermined limits regardless of output load on said buffer, said method comprising,
Dependencies are inferred from the claim text.