CMOS output circuit with high speed high impedance mode

In an output circuit for outputting an output signal having a given potential level in response to a potential level of an input signal having first and second potential levels, said output signal being permitted to be in high impedance state in response to a first potential level of a reset control signal having first and second potential levels, said output circuit comprising:

• a first control circuit outputting a first output control signal in response to said input signal at the time when said reset control signal has the second potential level;
• a second control circuit outputting a second output control signal in response to said input signal at the time when said reset control signal has the second potential level and also outputting a third output control signal at the time delayed by a first time counting from the outputting of the second output control signal, said second control circuit having a function to stop the outputting of said second output control signal in response to the change of potential level of said reset control signal from its second potential level to its first potential level and also a function to stop the outputting of said third output control signal substantially at the same time as the stoppage of the outputting of the second output control signal or at the time delayed by a second time which is shorter than the first time;
• and
• first, second and third switching circuits, said first switching circuit being connected between a third potential supply source and an output terminal and operative in response to said first output control signal, said second switching circuit being connected between a fourth potential supply source and said output terminal and operative in response to said second output control signal, and said third switching circuit being connected between a fourth potential supply source and said output terminal and operative in response to said third output control signal.

An output circuit for outputting an output signal having a given potential level in response to a potential level of an input signal having first and second potential levels, said output signal being in a high impedance state in response to a first potential level of a reset control signal having first and second potential levels, said output circuit comprising:

• a first control circuit for outputting a first output control signal in response to said input signal when said reset control signal has the second potential level, said first control circuit having a boosting circuit which is operative when said reset control signal has the second potential level, said boosting circuit outputting said first output control signal having a potential level which is higher than a power potential at the time when said input signal is in the second potential level;
• a second control circuit outputting a second output control signal in response to said input signal when said reset control signal has the second potential level, and for outputting a third output control signal at a time delayed by a first term counting from the outputting of the second output control signal, said second control circuit stopping said second output control signal when said reset control signal is changed from the second potential level to the first potential level, said second control circuit including a delay circuit which is operative when said reset control signal has the second potential level, said delay circuit receiving said second output control signal when said input signal is in the first potential level and outputting a delay signal at a time delayed by a given time interval from the reception of said second output control signal, and a third output control circuit for outputting said third output control signal at the time delayed by said given time interval in response to said second output control signal and said delay signal, said third output control circuit stopping the outputting of said third output control signal from said third output control circuit substantially at the same time as the stoppage of the outputting of the second output control signal or at a time delayed by a time interval which is shorter than the given time interval in response to only the change of the potential level of said second output control signal when said reset control signal is changed from the second potential level to the first potential level;
• first, second and third switching circuits, said first switching circuit being connected between a third potential supply source and an output terminal and operative in response to said first output control signal, said second switching circuit being connected between a fourth potential supply source and said output terminal and operative in response to said second output control signal, and said third switching circuit being connected between a fourth potential supply source and said output terminal and operative in response to said third output control signal.