System for interfacing wafer sort prober apparatus and packaged IC handler apparatus to a common test computer

An apparatus for interfacing a wafer sort prober apparatus or a packaged IC handler apparatus to a common test computer, said wafer sort prober apparatus for providing electrical connections to a semiconductor wafer, said packaged IC handler apparatus for providing electrical connections to a packaged integrated circuit, and said common test computer for controlling test operations performed upon said semiconductor wafer and said packaged integrated circuit, said interfacing system comprising:

• a mother interface board including a computer system interface area, a prober apparatus interface area, and a daughter board interface area, wherein said computer system interface area includes a plurality of contact pads for providing electrical connections to said test computer, wherein said prober apparatus interface area includes a plurality of contact pads for providing electrical connections to said wafer sort prober apparatus, wherein said daughter board interface area includes a plurality of female receptacles, and wherein said mother interface board includes an open hole positioned at a center portion of said mother interface board;
• and
• a daughter board including a plurality of male pins removably mated with said plurality of female receptacles included with said daughter board interface area of said mother interface board, and including a connector portion that mates with said packaged IC handler apparatus.

An apparatus for interfacing a packaged IC handler apparatus to a test head of a test system, said interfacing system comprising:

• a mother interface board having a plurality of first contactors to electrically contact said test head, a plurality of second contactors, and interface circuitry coupled between said first and second contactors;
• an IC contactor attached to said IC handler apparatus and having a plurality of third contactors;
• and
• a daughter board having a plurality of fourth contactors and a plurality of fifth contactors, said fourth contactors removably contacting said second contactors and said fifth contactors contacting said third contactors.

An apparatus for interfacing a probe card and a packaged IC contactor unit to a common test system at different times, said common test system having a test head with a plurality of first contact pins, said apparatus comprising:

• a mother interface board having:
• a plurality of first contact pads to contact said first contact pins and thereby electrically couple said mother interface board to said test head;
• a plurality of second contact pads;
• a plurality of first female receptacles;
• and
• an interior edge defining an open hole positioned at the center thereof;
• and
• an integrated circuit test unit removably coupled to said mother interface board, said integrated circuit test unit being one of a probe card and a packaged IC test unit, said probe card including a plurality of second contact pins, and said packaged IC test unit including:
• a daughter board having a plurality of second female receptacles and a plurality of first male pins;
• and
• an IC contactor having a plurality of second male pins removably mated with said second female receptacles to electrically couple and mechanically attach said IC contactor to said daughter board;
• wherein said second contact pads are contacted by said second contact pins when a wafer probe card is being interfaced, and wherein said first male pins are removably mated with said first female receptacles when a packaged IC test unit is being interfaced.

A common interface board for interfacing a probe card or a packaged IC contactor to a common test system, wherein said common test system includes a test computer and a test head with a plurality of first contactors that provide electrical coupling to said test computer, and wherein said probe card has a plurality of second contactors that provide electrical coupling to said common interface board, said common interface board comprising:

• a test head interface area on a first side of said common interface board, said test head interface area having a plurality of third contactors to contact said first contactors on said test head;
• a probe card interface area on a second side of said common interface board, said probe card interface area having a plurality of fourth contactors to contact said second contactors on said probe card;
• a daughter board interface area on said second side of said common interface board, said daughter board interface area having a plurality of fifth contactors;
• a plurality of electronic components coupling said third contactors to said fourth and said fifth contactors, wherein said electronic components are interconnected to form interface circuitry specific to a particular integrated circuit under test, the integrated circuit under test being one of die on a semiconductor wafer and a packaged chip;
• and
• an open hole that allows visual access to the semiconductor wafer when a wafer is positioned beneath said common interface board.

A method of using a common test system to test a device under test selected from a variety of integrated circuit devices, including integrated circuit dies and packaged integrated circuits, comprising:

• electrically coupling first terminals of interface circuitry on a mother interface board to the test system;
• selecting a contactor for the device under test, the contactor being a probe card when the device under test is an integrated circuit die, and the contactor being a packaged IC contactor when the device under test is a packaged integrated circuit;
• electrically coupling second terminals of the interface circuitry on the mother interface board to the probe card when the device under test is an integrated circuit die on a wafer;
• electrically coupling the second terminals of the interface circuitry on the mother interface board to a daughter board when the device under test is a packaged integrated circuit;
• and
• electrically coupling the daughter board to the packaged IC contactor when the device under test is a packaged integrated circuit.