US 5,489,795 AGranted

Semiconductor integrated circuit device having double well structure

AssigneeKabushiki Kaisha Toshiba

InventorsHisao Yoshimura, Takeo Maeda, Masakazu Kakumu

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions. The depth of the third well region is such that a depletion layer extending below the gate electrode (5) of the PMOS FET can be connected to a depletion layer formed at the interface between the third and fourth well regions.

Claims6

Dependent claims

A semiconductor integrated circuit device, comprising:

a semiconductor substrate of a first conductive type;
a first well region of a second conductive type, formed on said semiconductor substrate;
a second well region of the first conductive type, formed on said semiconductor substrate so as to form under said first well region;
a third well region of the first conductivity type, formed on said semiconductor substrate;
a fourth well region of the second conductive type, formed on said semiconductor substrate so as to form under said third well region;
a first MOS field effect transistor of the first conductive type formed in said first well region and having a first gate electrode formed on a first gate insulating film;
a second MOS field effect transistor of the second conductive type formed in said third well region and having a second gate electrode formed on a second gate insulating film;
means formed on said first well region and said third well region respectively, for applying a bias voltage;
and
said first well region being adjoining to said fourth well region;
and a depth of said first well region under the first gate electrode of said first MOS field effect transistor of the first conductive type from a surface of said semiconductor substrate being such that a first depletion layer extending from an interface between the first gate insulating film and said first well region is connected to a depletion layer formed at an interface between said first well region and said second well region and further a depth of said third well region under the second gate electrode of said second MOS field effect transistor of the second conductive type from the surface of said semiconductor substrate being such that a second depletion layer extending from an interface between the second gate insulating film and said third well region is connected to a depletion layer formed at an interface between said third well region and said fourth well region.

8 more elements

A semiconductor integrated circuit device, comprising:

a semiconductor substrate of a first conductive type;
a first well region of a second conductive type, formed on said semiconductor substrate;
a second well region of the first conductive type, formed on said semiconductor substrate;
a third well region of the second conductivity type, formed on said semiconductor substrate so as to form under said second well region;
a first MOS field effect transistor of the first conductive type formed in said first well region and having a first gate electrode formed on a first gate insulating film;
a second MOS field effect transistor of the second conductive type formed in said second well region and having a second gate electrode formed on a second gate insulating film;
means formed on said first well region and said second well region respectively, for applying a bias voltage;
and
said first well region being adjoining to said third well region;
and a depth of said first well region under the first gate electrode of said first MOS field effect transistor of the first conductive type from a surface of said semiconductor substrate being such that a first depletion layer extending from an interface between the first gate insulating film and said first well region is connected to a depletion layer formed at an interface between said first well region and said semiconductor substrate and further a depth of said second well region under the second gate electrode of said second MOS field effect transistor of the second conductive type from the surface of said semiconductor substrate being such that a second depletion layer extending from an interface between the second gate insulating film and said second well region is connected to a depletion layer formed at an interface between said second well region and said third well region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/317,835Filed 4 Oct 1994 · continuation
Priority: JP 4-23537211 Aug 1992
Granted: 6 Feb 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/021
Manufacture or treatment: of interconnections within wafers or substrates
H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
H10W 10/0127
Introducing electrical active impurities in local oxidation regions to create channel stoppers: using both n-type and p-type impurities, e.g. for…
H10W 10/13
Isolation regions comprising dielectric materials: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation…