Insulated gate semiconductor device with improved short-circuit tolerance

An insulated gate semiconductor device comprising:

• (a) a semiconductor body comprising:
• (a-1) a first semiconductor region of a first conductivity type exposed at a top major surface of said semiconductor body;
• (a-2) a second semiconductor region of a second conductivity type selectively formed in a top surface portion of said first semiconductor region and selectively exposed at said top major surface of said semiconductor body;
• (a-3) a third semiconductor region of the first conductivity type selectively formed in a top surface portion of said second semiconductor region and exposed at said top major surface of said semiconductor body on the inside of a peripheral edge portion of the exposed surface of said second semiconductor region,
• wherein said third semiconductor region defines a pattern on said top major surface of said semiconductor body, said pattern including a pair of strip areas arranged in parallel separately by a central area;
• (a-4) a fourth semiconductor region of the second conductivity type having an impurity concentration higher than an impurity concentration of said second semiconductor region and selectively formed in a top surface portion of said semiconductor body so as to surround said third semiconductor region, said fourth semiconductor region comprising:
• a first portion exposed at said top major surface of said semiconductor body in said central area and extending beneath the third semiconductor region;
• and
• a second portion exposed at said top major surface of said semiconductor body in an external area selectively defined on the outside of said pair of strip areas only at selected portions along the outside of said pair of strip areas;
• (b) an insulating layer selectively formed on said top major surface of said semiconductor body and having an opening on a predetermined region covering part of said pair of strip areas and at least part of said central area;
• (c) a control electrode layer buried in said insulating layer and opposed to the exposed surfaces of said second semiconductor region and said second portion of said fourth semiconductor region between said pair of strip areas of said third semiconductor region and the exposed surface of said first semiconductor region;
• (d) a first main electrode layer formed in said opening and electrically connected to a portion of said top major surface of said semiconductor body exposed in said opening;
• and
• (e) a second main electrode layer formed on a bottom major surface of said semiconductor body and electrically connected to said semiconductor body.