HF vapor surface treatment for the 03 teos gap filling deposition

A method of manufacturing an integrated circuit comprising:

• providing semiconductor device structures in and on a semiconductor substrate wherein the top surfaces of said semiconductor device structure are planarized;
• depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer;
• conformally depositing a first TEOS oxide layer over the surfaces of patterned said conducting layer wherein a gap of greater than 1800 Angstroms remains between portions of said first TEOS oxide layer covering said patterned conducting layer;
• treating the surface of said first TEOS oxide layer with HF vapor whereby SiOF molecules are formed on the surface of said first oxide layer;
• depositing a second oxide TEOS layer over said first TEOS oxide layer wherein the presence of said SiOF molecules improves the step coverage of said second TEOS oxide layer so that said gap is filled by said second TEOS oxide layer;
• and
• completing the fabrication of said integrated circuit.

A method of manufacturing an integrated circuit comprising:

• providing semiconductor device structures in and on a semiconductor substrate wherein the top surfaces of said semiconductor device structures are planarized;
• depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer;
• conformally depositing a first TEOS oxide layer over the surfaces of said conducting layer wherein a gap is formed between portions of said patterned conducting layer;
• treating the surface of said first TEOS oxide layer with HF vapor at a flow rate of between about 0.5 to 5 slm under a pressure of between about 150 to 500 Torr for a duration of between about 10 to 50 seconds whereby SiOF molecules are formed on the surface of said first TEOS oxide layer;
• depositing a second TEOS oxide layer over said first TEOS oxide layer wherein the presence of said SiOF molecules improves the step coverage of said second TEOS oxide layer so that said gap is filled by said second TEOS oxide layer;
• and
• completing the fabrication of said integrated circuit.