Flexible strip structure for a parallel processor and method of fabricating the flexible strip

A method of fabricating a parallel processor structure having a plurality of processor integrated circuit chips, a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein

• a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon;
• b. said printed circuit cards and boards are mounted on a plurality of circuitized flexible strips, said circuitized flexible strips comprising at least one 1S1P ply having an internal signal core, and internal power core, and a layer of dielectric therebetween, and having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and
• c. said circuitized flexible strips being joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible strips at their signal interconnection circuitization portions, whereby said circuitized flexible strips are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions;
• said process comprising
• 1). forming a laminate of a Cu signal plane, a conductive power plane, and a layer of dielectric therebetween;
• 2). depositing photoresist on both surfaces of said laminate;
• 3). imaging the photoresist to define fiducials, vias, and through holes thereon;
• 4). forming clearance holes for vias and through holes in the power and signal planes of the laminate;
• 5). applying dielectric sheets atop exposed metal surfaces of the laminate to thereby relaminate the laminate;
• 6). drilling signal and power through holes and vias through the laminate;
• 7). circuitizing the signal and power vias of the laminate;
• 8). laminating a pair of laminates to form a 2S2P circuitized flex circuit;
• and
• 9). stacking a plurality of circuitized flex circuits, and compressing and bonding only center portions thereof to form a package with X, Y, and Z axis circuitization.