Multiple concurrent display system

A display subsystem providing for the simultaneous redisplay of independent images to multiple independent display devices, said display subsystem comprising:

• a) a video memory storage unit providing for the storage and retrieval of pixel data in response to address control signals, said pixel data including a first display image and a second display image, said pixel data corresponding to said first display image being interleaved with said pixel data corresponding to said second display image;
• b) a first display interface providing for the transfer of first display control and data signals;
• c) a second display interface providing for the transfer of second display control and data signals;
• d) a data buffer coupled to said video memory storage unit and coupleable to an external data bus to permit the direct transfer of data between said external data bus and said video memory storage unit;
• and
• e) a video controller coupled to said video memory storage unit, said data buffer, and to said first and second display interfaces, said video controller generating said addressing signals to retrieve said pixel data in a sequential address sequence, said video controller further generating said first and second display and control signals from respective subsets of said pixel data corresponding to said first and second display images.

A computer system providing for the simultaneous independent display of computer images on a plurality of independent video output devices, said computer system comprising:

• a) an addressable video data memory providing for the storage of register control data in a first memory area and image data in a second memory area;
• b) a first interface coupleable to a first video output device;
• c) a second interface coupleable to a second video output device;
• and
• d) an integrated circuit coupled to said video data memory, said integrated circuit including:
• i) control means for addressing said video data memory to transfer said register control data and said image data between said video data memory and said control means, said control means providing for the logical establishment of first and second sets of said register control data in said first memory area, said control means providing for the mutually interleaved storage of predetermined sub-portions of first and second image data sets in said second memory area, said control means further providing for the sequential addressing of said second memory area to store and retrieve respective interleaved sub-portions of said first and second image data sets;
• ii) sequencer means, responsive to the interleave of said sub-portions as provided said control means, for sequentially providing said respective sub-portions of said first and second image data sets separately to said first and second interfaces;
• and
• iii) buffer means for providing a first data path between said video data memory and said control means, a second data path between said video data memory and said sequencer means, and a third data path between said video data memory and an external data interface.