Data processing system for hardware implementation of square operations and method therefor

A memory system for use with at least one information requesting device comprising:

• first and second memory portions;
• a controller for receiving first and second input addresses and for providing first and second memory addresses to said first and second memory portions, respectively, in response, each of said first and second input addresses having a first portion and a second portion;
• multiplex means coupled to said first and second memory portions, for multiplexing data from said first memory portion onto either said first or said second data path in response to said first portion of said first input address, and from said second memory portion onto either said first or said second data path in response to said first portion of said second input address;
• and
• logic means, for activating a wait signal which causes said at least one information requesting device to delay an access to said second data path if both, said first portion of said first input address and said first portion of said second input address are equal, and, said second portion of said first input address and said second portion of said second input address are not equal, and for keeping said wait signal inactive if, said first portion of said first address and said first portion of said second address are equal and said second portion of said first address and said second portion of said second address are equal.

In a data processing system including a memory system and a data processor, the data processor coupled to first and second data paths and first and second addresses corresponding thereto, respectively, the memory system comprising:

• first and second memory portions;
• multiplex means coupled to said first and second memory portions, for multiplexing data from said first memory portion onto either said first or said second data path in response to a first portion of the first address, and from said second memory portion onto either said first or said second data path in response to a first portion of the second address;
• and
• logic means coupled to said multiplex means and to the data processor, for activating a wait signal which causes said data processor to delay an access to said second data path if both, said first portion of the first address and said first portion of the second address are equal, and, a second portion of the first address and a second portion of the second address are unequal, and for keeping said wait signal inactive if, said first portion of said first address and said first portion of said second address are equal and said second portion of said first address and said second portion of said second address are equal.

A data processing system comprising:

• a data processor coupled to first and second data paths and first and second addresses corresponding thereto, respectively, each of said first and second addresses having a first portion and a second portion, said data processor delaying an access to said second data path in response to a wait signal being active;
• first and second memory portions;
• a first multiplexer coupled to said first and second memory portions and to said first data path, for coupling either said first or said second memory portion to said first data path in response to said first portion of said first address being in first or second states thereof, respectively;
• a second multiplexer coupled to said first and second memory portions and to said second data path, for coupling either said first or said second memory portion to said second data path in response to said first portion of said second address being in first or second states thereof, respectively;
• control means coupled to said data processor, for providing a first memory address to either said first memory portion if said first portion of said first address is in said first state, or to said second memory portion if said first portion of said first address in said second state, and for providing a second memory address to either said first memory portion if said first portion of said second address is in said first state, or to said second memory portion if said first portion of said second address in said second state;
• and
• logic means coupled to said data processor, for activating said wait signal if both, said first portions of said first and second addresses are equal, and said second portions of said first and second addresses are unequal, and for keeping said wait signal inactive if, said first portion of said first address and said first portion of said second address are equal and said second portion of said first address and said second portion of said second address are equal.

A method of improving performance of a data processing system comprising the steps of:

• providing first and second addresses each having first and second portions for accessing data via first and second data paths, respectively, in response to a plurality of instructions;
• accessing first and second data elements respectively in response to said first and second addresses, said first data element accessed from either a first memory portion or a second memory portion in response to said first portion of said first address, said second data element accessed from either said first memory portion or said second memory portion in response to said first portion of said second address;
• multiplexing data from one of said first and second memory portions selected in response to said first portion of said first address, onto said first data path;
• multiplexing data from one of said first and second memory portions selected in response to said first portion of said second address, onto said second data path;
• and
• either, reading said first data element via said first data path and said second data element via said second data path if said first portion of said first and second addresses are not equal, or
• reading said first data element via said first data path during a first memory cycle and said second data element via said second data path during a second memory cycle if said first portion of said first and second addresses are equal and a second portion of said first and second addresses are not equal, or
• reading said first data element via said first and second data paths during said first memory cycle if both, said first portions of said first and second addresses are equal, and said second portions of said first and second addresses are equal.