US 5,487,022 AGranted

Normalization method for floating point numbers

AssigneeTexas Instruments Incorporated

InventorsRichard Simpson, Erick D. Oakland, Graham M. Barr

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Abstract

A floating point normalization circuit and method decodes the exponent generating a coded multibit output corresponding to the maximum decrease in the exponent within the minimum expressible exponent. This coded multibit output is bit-wise ORed with the mantissa. A left most one circuit detects the bit position of the most significant bit of the logical OR output having a "1". The mantissa and exponent are them normalized according to this number. The mantissa is left shifted an amount equal to this detected bit position of a most significant bit having a "1". The exponent is decremented an amount equal to this detected bit position of a most significant bit having a "1". The exponent decoder generates said coded multibit output in the form of a mantissa equal to the minimum mantissa that can be normalized for the input exponent part of the floating point number. This minimum mantissa is equal to 2.sup.(M+N), where M is the minimum expressible exponent and N is the exponent. In the preferred embodiment, the exponent decoder includes a two to four line decoder for each pair of bits of the exponent part of the floating point number, and an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa.

Claims6

Dependent claims

A floating point normalization circuit receiving a mantissa part and an exponent part of a floating point number, the exponent part having a minimum expressible exponent, said circuit comprising:

an exponent decoder receiving the exponent part of the floating point number and generating a coded multibit output corresponding to a maximum decrease in the exponent part of the floating point number within the minimum expressible exponent, said exponent decoder including
a two to four line decoder for each pair of bits of the exponent part of the floating point number, and
an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa;
a bit-wise OR circuit connected to said exponent decoder, receiving the mantissa part of the floating point number and said coded multibit output and forming a logical OR output of each bit of the mantissa part with a corresponding bit of said coded multibit output;
a left most one circuit connected to said bit-wise OR circuit detecting a bit position of a most significant bit of said logical OR output having a "1";
a left shifter circuit connected to said left most one circuit and receiving the mantissa part of the floating point number, said left shifter left shifting the mantissa part the floating point number an amount equal to said detected bit position of a most significant bit having a "1";
and
a decrementer connected to said left most one circuit and receiving the exponent part of the floating point number, said decrementer decrementing the exponent part of the floating point number an amount equal to said detected bit position of a most significant bit having a "1".

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Dependencies are inferred from the claim text.