ECL to CMOS converter

A logic converter comprising:

• a differential amplifier for receiving and differentially amplifying an input signal, said differential amplifier having a first differential input node coupled to said input signal, and a second differential input node coupled to a reference voltage source;
• a first emitter follower coupled to a first output node of said differential amplifier, said first emitter follower producing a first intermediate signal in response to said input signal;
• a second emitter follower coupled to a second output node of said differential amplifier, said second emitter follower producing a first complementary intermediate signal in response to said input signal;
• a regenerative stage coupled to said first and second emitter followers, said regenerative stage having a first and a second pull-down portion for generating a second pair of complementary, intermediate signals on corresponding first and second output nodes by switching between a partially on state and a fully on state in response to said first intermediate signal and said first complementary, intermediate signal;
• a first inverter stage having a first input node coupled to said first emitter follower, and a second input node coupled to said second output node of said regenerative stage, and wherein said first inverter stage provides a third intermediate signal in response to said first intermediate signal and said second complementary intermediate signal;
• a second inverter stage having a first input node coupled to said second emitter follower, and a second input node coupled to said first output node of said regenerative stage, and wherein said second inverter stage provides a third complementary intermediate signal in response to said first complementary intermediate signal and said second intermediate signal;
• a first output driver stage coupled to said first and second inverter stages for generating a first output signal in response to said third intermediate and said third complementary intermediate signals;
• and
• a second output driver stage coupled to said first and second inverter stages for generating a second output signal in response to said third intermediate and said third complementary intermediate signals.