Semiconductor memory having a plurality of banks usable in a plurality of bank configurations

A semiconductor memory having 2.sup.x banks, where x is an integer equal to or greater than two, that maintain an active state if required even under an unselected state after a read or write operation, any memory cell in any one of said banks being selectable according to a first address signal and a second address signal successively provided to said semiconductor memory, wherein said semiconductor memory comprises:

• a first specify means for decoding an x-bit bank address signal contained in said first address signal, to specify one of said 2.sup.x banks functioning as they are or as 2.sup.y banks, where y is an integer equal to or greater than one and obtained by dividing the x by a multiple of two, so that a word line is selected in said specified bank;
• and
• a second specify means for decoding, according to indicating whether or not each of said 2.sup.x banks is active, an x-bit bank address signal contained in said second address signal if said 2.sup.x banks function as they are or a y-bit bank address signal contained in said second address signal if said 2.sup.x banks functional as 2.sup.y banks, to specify the bank that has been specified according to said first address signal, so that data are written into or read out of said specified bank.