Electronic control system having master/slave CPUs for a motor vehicle
AssigneeFuji Jukogyo Kabushiki Kaisha
InventorAkira Ogura
Life of this patent
Estimating the term…
Loading patent…
AssigneeFuji Jukogyo Kabushiki Kaisha
InventorAkira Ogura
Estimating the term…
An electronic control system for a motor vehicle, having multiple sensors (M1) for detecting the operating condition parameters of the motor vehicle; a master controller (M4) from and to which communication lines are laid; and a plurality of slave controllers (M2) which convert the operating condition parameters detected by the sensors (M1) and various data items processed in the control system, into serial data items and transmit them to the master controller (M4) through the communication lines, and which control a plurality of components (M3) installed on the motor vehicle, on the basis of data items received from the master controller (M4); the master controller (M4) being connected with the plurality of slave controllers (M2) through the communication lines, to calculate controlling data items on the basis of various data items received as inputs from the respective slave controllers (M2), and converting the controlling data items into the serial data items and transmitting them to the respective slave controllers (M2) through the communication lines.
An electronic control system for a motor vehicle having, a plurality of parameter detecting means for sensing operating conditions of said motor vehicle and for generating an operating condition signal, and a plurality of actuating means for controlling said motor vehicle, the system comprising:
An electronic control system for a motor vehicle having, a plurality of parameter detecting means for sensing operating conditions of said motor vehicle and for generating an operating signal, and a plurality of actuating means for controlling said motor vehicle, the system comprising:
A electronic control system for a motor vehicle which provides a plurality of equipment controlled by each electric controller having a microprocessor, a memory, an I/O interface and a bus-line connecting said microprocessor, said memory and said I/O interface with each other, the system comprising:
Dependencies are inferred from the claim text.