Method and apparatus for switching clock signals in a fault-tolerant computer system
AssigneeStratus Computer, Inc.
InventorsDavid R. Barbera, Franklin M. Savicki, David E. Splitz
Life of this patent
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Abstract
A clock switching circuit switches between clock signals generated by a local clock unit and those generated by a-system clock unit when disabling, and then subsequently enabling, the system clock unit. The clock switching circuit includes a plurality-of switching circuits that are arranged and configured to switch between the system and local clock units so as to provide a substantially uninterrupted stream of clock signals to selected components of a fault-tolerant computer system. This arrangement ensures that information stored on the selected components is not lost during disablement of the system clock unit.
Claims18
A clock switching circuit for switching between clock signals generated by one of a local clock unit and a system clock unit when disabling and subsequently enabling the system clock unit, said clock switching circuit comprising:
- a first multiplexer configured to pass one of system clock signals generated by the system clock unit and logical ground signals onto output lines of said first multiplexer;
- a second multiplexer configured to pass one of local clock signals generated by a local clock unit and logical ground signals onto output lines of said second multiplexer, said first and second multiplexers being further configured such that one of said system and local clock signals pass onto said output lines;
- a third multiplexer arranged to receive one of said system and local clock signals from said output lines coupled to first and second sets of input lines of said third multiplexer, said third multiplexer further configured to couple one of said first and second sets of input lines to third output lines of said third multiplexer for passing one of said system and local clock signals onto said third output lines;
- and
- clock control means for generating enable signals that configure said third multiplexer to switch from said one of said sets of input lines to the other of said sets of input lines so as to pass the other of said system and local clock signals onto said third output lines without adversely impacting the integrity of said clock signals passing through said third multiplexer.
A remote connector unit configured to receive power-down and power-up commands for respectively disabling and enabling a system clock unit of a fault-tolerant computer, said system clock unit configured to deliver a stream of system clock pulses at an output thereof, said remote connector unit comprising:
- a processor for generally controlling the operations of said remote connector unit;
- bus interface logic coupled to said processor and containing a plurality of addressable registers;
- a local clock unit for generating a stream of local clock pulses;
- and
- clock selecting means, coupled between said bus interface logic and said local clock unit, for receiving said streams of local and system clock pulses and for selecting between said streams to provide one of said local and system clock pulses to said bus interface logic.
A method for disabling and subsequently enabling a system clock unit of a fault-tolerant computer in response to respective power-down and power-up commands received at a remote connector unit of the computer, said method comprising the steps of:
- generating a first stream of local clock pulses at a local clock unit and a second stream of system clock pulses at a system clock unit;
- receiving said first ;and second streams of clock pulses at a clock switching circuit;
- selecting said first stream and passing said local clock pulses to an output of said clock switching circuit in response to an enable selection signal generated by a clock control circuit;
- scanning said stream of system clock pulses at a clock-fault circuit to detect a pulse transition;
- deasserting a clock-fault signal at said clock-fault circuit in response to detection of said pulse transition;
- and
- switching from said first stream to said second stream and passing said system clock pulses to said output of said clock switching circuit in response to an inverted enable selection signal generated by said clock control circuit.
Dependencies are inferred from the claim text.