Method and apparatus for obtaining data from a data circuit utilizing alternating clock pulses to gate the data to the output

In a data processing system including a random access memory, a master clock, and a data clock, wherein the master clock generates master clock pulses having a selected frequency, each master clock pulse having a leading edge and a trailing edge, wherein the data clock generates a first data clock signal corresponding to the leading edge of each master clock pulse for accessing the memory and a second data clock signal corresponding to the trailing edge of each master clock pulse for accessing the memory, wherein the memory produces a first data signal on the output node in response to the first data clock signal and a second data signal on the output node in response to the second data clock signal, and wherein the memory has a selected delay between the time a data clock signal initiates access of the memory and the time the data appears at the output node, an apparatus for retrieving data from the memory comprising:

• a first memory element for storing data signals from the output node;
• a second memory element for storing data signals from the output node;
• and
• signal storing means having means for producing first and second delayed data clock signals that have a delay less than the selected delay of the memory, coupled to the memory, to the first memory element, and to the second memory element, for storing the first data signal in one of the first memory element or second memory element in response to the first delayed data clock signal and for storing the second data signal in the other first memory element or second memory element in response to the second delayed data clock signal.

An apparatus for obtaining data from a data circuit having a selected delay between the time a clock pulse initiates functioning of the circuit and the time the data appears at an output node of the circuit comprising:

• master clock means for generating master clock pulses having a selected frequency, each clock pulse having a leading edge and a trailing edge;
• data clock means for generating a first data clock pulse corresponding to the leading edge of each master clock pulse, and for generating a second data clock pulse corresponding to the trailing edge of each master clock pulse;
• wherein the data circuit is coupled to the data clock means for receiving the data clock pulses therefrom, the data circuit generating a first data signal at the output node in response to the first data clock pulse, and the data circuit generating a second data signal at the output node in response to the second data clock pulse;
• a first memory element for storing data signals from the data circuit;
• a second memory element for storing data signals from the data circuit;
• and
• signal storing means, coupled to the data clock for receiving the first and second data clock pulses, to the data circuit, to the first memory element, and to the second memory element, for storing the first data signal in one of the first memory element or second memory element in response to the first data clock pulse and for storing the second data signal in the other first memory element or second memory element in response to the second data clock pulse.

In a memory system including a random access memory having a first output node which produces an active signal representing a selected data logic level and a second output node which produces an active signal representing a complementary data logic level, an apparatus for retrieving data from the memory comprising:

• master clock means for generating master clock pulses having a selected frequency, each clock pulse having a leading edge and a trailing edge;
• data clock means for generating a first data clock pulse corresponding to the leading edge of each master clock pulse, and for generating a second data clock pulse corresponding to the trailing edge of each master clock pulse;
• wherein the memory is coupled to the data clock means for receiving the data clock pulses therefrom;
• wherein the memory produces first data signals on the first and second output nodes in response to the first data clock pulse and second data signals on the first and second output nodes in response to the second data clock pulse;
• wherein the memory has a selected delay between the time a data clock pulse initiates access of the memory and the time the data appears at the first and second output nodes;
• a first memory element for storing data signals from the first and second output nodes;
• a second memory element for storing data signals from the first and second output nodes;
• and
• signal storing means, coupled to the memory, to the first memory element, and to the second memory element, for storing the first data signals in one of the first memory element or second memory element in response to the first data clock pulse and for storing the second data signals in the other first memory element or second memory element in response to the second data clock pulse.

A method for obtaining data from a data circuit having a selected delay between the time a clock signal initiates functioning of the circuit and the time the data appears at an output node of the circuit comprising the steps of:

• receiving, by the data circuit, first and second clock signals from a clock signal source;
• generating corresponding first and second data signals at the output node in response to the first and second clock signals and at a time consistent with the selected delay;
• propagating the first clock signal through a first delay element for producing a first delayed clock signal for gating the first data signal to a first or second memory element, the first delay element having a delay less than the selected delay;
• propagating the second clock signal through a second delay element for producing a second delayed clock signal for gating the second data signal to a first or second memory element, the second delay element having a delay less than the selected delay;
• storing the first data signal in one of the first memory element or second memory element in response to the first delayed clock signal;
• and
• storing the second data signal in the other first memory element or second memory element in response to the second delayed clock signal.