Portable computer capable of switching CPU clocks

A portable computer comprising:

• a microprocessor including a clock generating section which has a clock register with a value of an internal clock frequency set therein and a frequency divider for generating the internal clock frequency by frequency-dividing a fundamental clock in accordance with the value set in said clock register;
• input means for outputting a command designating an increase or a decrease, in response to a key operation;
• and
• changing means, connected to said input means and said microprocessor, for updating the value set in said clock register to change the value of the internal clock frequency, in accordance with the command outputted from said input means.

An apparatus for selectively generating a clock for computer operations based on input of an operator, the apparatus comprising:

• at least one clock register for storing a frequency value;
• frequency dividing means for receiving an externally supplied primary clock signal, for frequency dividing the primary clock signal to generate at least one secondary clock signal having a frequency equal to the frequency value in the at least one clock register, and for outputting the secondary clock signal;
• first input means for receiving a first input from the operator and outputting a first signal in response to the first input;
• second input means for receiving a second input from the operator and outputting a second signal in response to the second input;
• and
• interrupt means for receiving the first and second input signals, and for outputting an interrupt signal in response to the first interrupt signal or the second interrupt signal;
• and
• a microprocessor for receiving the interrupt signal, for receiving the first and second input signals in response to the interrupt signal, for increasing the frequency value stored in the at least one clock register in response to the first input signal, and for decreasing the frequency value stored in the at least one clock register in response to the second input signal.

A process for generating a clock for computer operations comprising the steps of:

• receiving input data from an operator by an input means, and outputting an input signal in response thereto;
• interrupting a microprocessor in response to the input signal;
• storing, when the microprocessor has been interrupted, a frequency value selected by a microprocessor according to the input signal, in a clock register;
• receiving, by a frequency dividing means, a primary clock;
• and
• generating a secondary clock with a frequency equal to the frequency value stored in the clock register, by frequency division of the primary clock by the frequency dividing means.