Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking
AssigneeIntel Corporation
InventorsJames Nadir, Ching-Hua Chu
Life of this patent
Estimating the term…
Abstract
A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity. The parity field is stored in a status array physically separate from the tag array. The status array is offset in timing so that it lags behind the tag array for both read and write operations. Therefore, fields in the status array can be written in the early part of the next clock cycle without affecting the tag array or another operation that may be scheduled for the next time cycle.
Claims14
In a computer processor, a cache circuit for one-cycle operation of cache read and cache write instructions, said cache circuit allowing writing operations of a first one of said cache instructions in a first cycle supplied by a main clock signal to be overlapped with a second one of said cache instructions in a second cycle immediately following the first cycle, said cache circuit including:
- a physical address means for providing a physical address having a plurality of fields including a tag address field, a byte offset field, and a set select field including set select data;
- a set associative cache having a plurality of sets, each set including one or more cache lines for storing computer data, each cache line associating a tag field, a status field, and a data field, said cache including
- a data array having a plurality of data fields,
- a tag array having a plurality of tag fields, and
- a status array having a plurality of status fields, each status field including a tag parity field indicative of the parity of the tag, and a valid field indicative of the validity of the data;
- a set select circuit coupled to the physical address means for decoding set select data of a physical address to select a set of cache lines;
- control means for providing a tag enable signal and also for providing a status enable signal delayed in timing from said tag enable signal;
- a plurality of tag drivers coupled to the set select circuit, each tag driver responsive to said selected set of cache lines and the tag enable signal, for enabling a tag field in the tag array;
- and
- a plurality of status drivers coupled to the set select circuit, each status driver being responsive to said selected set of cache lines and the status enable signal, for enabling a status field in the status array.
In a computer processor whose operations are defined by a series of clock cycles, a method of writing a tag address and its associated parity information to a cache having a tag array, a status array, and a data array, said cache having a plurality of cache lines for storing computer data, each cache line associating a data field in a data array with a tag field in the tag array, and a status field including a tag parity field in the status array, said method comprising the steps of:
- (a) supplying a decoder with a physical address to be written, including a tag address, a set select field including set select data, and a byte offset;
- (b) decoding said set select data to select a cache line;
- (c) enabling a tag field associated with the selected cache line in the tag array;
- (d) writing said tag address to said enabled tag field;
- (e) generating a parity bit indicative of the parity of said tag address;
- (f) subsequently to said step (c), enabling a status field associated with the selected cache line in the status array;
- and
- (g) writing the parity bit generated in said step (e) to the parity field in said enabled status field.
In a computer processor for executing instructions timed with a series of clock cycles, a method for accessing a cache line for reading or writing, and calculating and checking the parity of tag data in the cache line, so that a read instruction or a write instruction can be performed each cycle, said method comprising the steps of:
- (a) supplying a first clock cycle and a second clock cycle next following the first clock cycle;
- (b) supplying a physical address including a tag address and a set select field;
- (c) if a read is requested, then in the first clock cycle executing the steps of
- (c)(1) selecting a first cache line,
- (c)(2) enabling a tag field of said first cache line,
- (c)(3) reading a tag from said enabled tag field,
- (c)(4) comparing the enabled tag field with the physical address to determine if there is a match,
- (c)(5) if a match is determined in step (c)(4), then supplying a tag match signal, first signal, and otherwise, supplying a second signal,
- (c)(6) checking the parity of the enabled tag field by generating a parity of the enabled tag field and comparing it with a predetermined parity stored in a status field of said first cache line,
- (c)(7) if the generated parity of said enabled tag field matches said predetermined parity, then supplying a parity match signal,
- (c)(8) determining a hit only if both the tag match signal and the priority match signal are provided, otherwise determining a miss,
- (d) if a write is requested by an instruction, then
- (d)(1) in the first clock cycle executing the steps of supplying a physical address including a tag address that selects a second cache line to be written to, and writing the tag address to the second cache line,
- (d)(2) in the first clock cycle and continuing into the second clock cycle, calculating the parity of the tag address to supply parity data and storing said parity data in said second cache line.
Dependencies are inferred from the claim text.