Flash memory mass storage architecture incorporation wear leveling technique

A non-volatile semiconductor mass storage device comprising:

• a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable and erasable;
• b. a first indicating element to provide a first indicia whether each block has been programmed with a data file;
• c. a second indicating element to provide a second indicia whether the data file of each programmed block is superseded;
• d. a programming element to program a new data file into an empty block;
• and
• e. a periodically activated erasing circuit coupled to each of the storage blocks for selectively erasing all blocks in which the data file is superseded, wherein the erasing circuit is not activated each time data is stored in one of the storage blocks;
• f. means for correlating coupled to the storage blocks and to the programming element for directly correlating a logical address assigned to superseded data to a physical address of updated data wherein the first indicating element, the second indicating element and the logical address are stored in a nonvolatile content addressable memory.

A non-volatile semiconductor mass storage device comprising:

• a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable;
• b. a plurality of first flags, one first flag for each block, each first flag having a first logic state to indicate that a block has not been programmed with data and a second logic state to indicate that the block has been programmed with data;
• c. a selecting element coupled to the storage blocks and to the plurality of first flags for identifying an empty storage block having a first flag in the first logic state where new and updated data may be stored;
• d. a plurality of second flags that can only be changed in a block having its first flag in the second logic state, one second flag for each block, each second flag having a third logic state to indicate that the data in a block is valid and a fourth logic state to indicate that the data in the block has been superseded;
• e. a content addressable memory for storing a logical address assigned to a block of superseded data and a physical address of a block of updated data corresponding to the superseded data;
• and
• f. an erasing circuit coupled to each of the storage blocks for selectively erasing all blocks having a second flag in the fourth logic state, wherein the erasing circuit is not activated each time data is stored in a storage block;
• and
• g. means for directly correlating coupled to the storage blocks and to content addressable memory, for correlating a logical address assigned to the superseded data to a physical address of updated data.

A method of storing data into a non-volatile semiconductor mass storage device having a plurality of non-volatile storage blocks, wherein each block is selectively programmable and erasable wherein only blocks containing no data may be programmed, the method comprising the steps of:

• a. determining whether any unprogrammed blocks remain;
• b. replacing superseded data with updated data by ignoring blocks having superseded data and programming the updated data into a block containing no data without erasing the superseded data;
• and
• c. periodically and selectively erasing all blocks having superseded data;
• d. directly correlating a logical address assigned to a block of superseded data to a physical address of a corresponding block of updated data.