Concurrent cache line replacement method and apparatus in microprocessor system with write-back cache memory

A microprocessor system comprising:

• a CPU;
• a main memory;
• a cache memory coupled to said CPU, said cache memory including a plurality of cache lines associated with addresses in said microprocessor system, and each cache line storing a plurality of data;
• a data path unit coupled to said CPU, and said main memory, said data path unit comprising a write buffer;
• a cache and main memory controller (CDC) coupled to said CPU, said cache memory, said main memory, and said data path unit, for controlling the operation of said cache memory and transfers of data from said CPU to said main memory and said cache memory, as well as, from said write buffer to said main memory, wherein said CDC, responsive to first predesignated conditions, simultaneously initiates writing of a first data of the plurality of data stored in a first cache line in said cache memory to said write buffer, and initiates reading of a second data from said main memory, such that, said first data is written from said first cache line to said write buffer, said second data is written into said first cache line at the location of the first data and to said CPU once the first data is written to the write buffer, said CDC continues to initiate writing of a next data from the cache line and simultaneously initiate reading of a next data from the main memory and once the next data is written to the write buffer writes the next data read to the cache line until the plurality of data stored in the first cache line is written to the write buffer and a plurality of data is read from main memory and written to the first cache line and said plurality of data are written from said write buffer to said main memory.

In a microprocessor system comprising a CPU, a cache memory coupled to said CPU, said cache memory including a plurality of cache lines associated with addresses in said microprocessor system, each cache line storing a plurality of data, and a DRAM, a concurrent cache line replacement apparatus comprising:

• data path unit (DPU) coupled to said CPU, and said DRAM, said DPU comprising a write buffer;
• and
• a cache and DRAM controller (CDC) coupled to said CPU, said cache memory, said DRAM, and said DPU, for controlling the operation of said cache memory and transfers of data from said CPU to said DRAM and said cache memory, as well as, from said DPU to said DRAM, wherein said CDC, responsive to first predesignated conditions, simultaneously initiates writing of a first data of the plurality of data stored in a first cache line in said cache memory to said write buffer, and initiates reading of a second data from said DRAM, such that said first data is written from said first cache line to said write buffer, said second data is written into said first cache line in said cache memory at the location of the first data and to said CPU once the first data is written to the write buffer, said CDC continues to initiate writing of a next data from the cache line and simultaneously initiate reading of a next data from the DRAM and once the next data is written to the write buffer writes the next data read to the cache line until the plurality of data stored in the first cache line is written to the write buffer and a plurality of data is read from DRAM and written to the first cache line, and the plurality of data are written from said write buffer to said DRAM.

In a microprocessor system comprising a CPU, a main memory, a write buffer coupled to said main memory, and a cache memory coupled to said CPU having cache lines associated with addresses in said microprocessor system, where each cache line comprises a plurality of groups of words, a concurrent cache line replacement method comprising the steps of:

• (i) initiating a read access of data at a first address;
• (ii) determining whether said read access is a cache miss, and further determining whether a particular cache line in said cache memory associated with said first address is a dirty line;
• and
• (iii) if said read access results in a cache miss, and said particular cache line is a dirty line then performing the following steps:
• (a) initiating writing of a group of a predetermined number of words of the dirty line in said cache memory to said write buffer, where the group of predetermined number of words contains at least one word and is smaller than the cache line;
• (b) simultaneously initiating reading words of a new line from said main memory;
• and
• (c) following the completion of said writing of the group of predetermined number of words of the dirty line to said write buffer performing the following steps:
• (1) providing a group of a predetermined number of words of said new line in response to the reading of the new line from said main memory, where the group of the predetermined number of words of said new line is equal in size to the group of the predetermined number of words of the cache line;
• and
• (2) writing the group of the predetermined number of words of said new line into said cache memory and to said CPU;
• (iv) upon completion of step iii(c), repeating step (iii)(a) and (iii)(c) until the dirty line is entirely written to the write buffer and the new line is entirely written to the dirty fine;
• and
• (v) writing the dirty line from said write buffer to said main memory.