US 5,479,630 AGranted

Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same

AssigneeSilicon Graphics, Inc.

InventorEarl A. Killian

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Abstract

A cache memory system includes a primary cache characterized by a virtual index and physical tags, and a secondary cache characterized by a physical index and physical tag. Thus, the cache system forms a hybrid of physical-cache and virtual-cache characteristics. Further, the secondary cache includes a primary index segment for each line of secondary cache. The primary index segment corresponds to a portion of the virtual address for the contents stored at the respective secondary-cache line. Further, primary cache is maintained as a subset of secondary cache. To maintain the primary cache in such a way, the primary index segment is used to generate an index into primary cache to identify each potential primary-cache block which may be a subset of a secondary-cache block to be changed. When a secondary-cache block is to be invalidated, flushed or overwritten, the corresponding primary-cache blocks are identified and invalidated. The primary index segment also serves as a virtual tag for assuring that at any given time primary cache stores no more than one valid block corresponding to the same physical locations. When a secondary-cache hit occurs in response to a secondary-cache physical tag check, the primary index segment is compared to a portion of the virtual address. If the segment does not match, then primary cache may already have a word stored which corresponds to the desired physical location. As a result, the corresponding block in primary cache is invalidated and the primary index segment in secondary cache is changed to the current virtual address segment.

Claims13

Dependent claims

A method, in a computing device having a processor, a main memory and a cache memory system having a primary cache and a secondary cache, said method for accessing said primary cache using an n-bit virtual address having a virtual page number and a page offset, comprising the steps of:

accessing an indexed primary-cache line using a virtual index, said primary cache line storing at least a first word, said virtual index being a first subset of the n bits forming said virtual address, said indexed primary-cache line storing a primary-cache physical tag;
translating said n-bit virtual address into a translated address, including a translated m-bit physical address;
comparing said primary-cache physical tag with a primary tag reference, said primary tag reference being a first subset of the m-bits forming said translated m-bit physical address;
accessing a secondary-cache line with a physical index in response to a mismatch between said primary-cache physical tag and said primary tag reference, said physical index being a second subset of the m bits forming said translated physical address, said secondary-cache line comprising a secondary-cache physical tag, a second word and a primary index segment;
checking said secondary-cache physical tag with a secondary tag reference to confirm a desired physical address is being accessed, said secondary tag reference being a third subset of the m-bits forming said translated physical address;
and
comparing said primary index segment to a primary index segment reference in response to a match between said secondary-cache physical tag and said secondary tag reference so to determine whether said second word is also addressed by said n-bit virtual address, said primary index segment reference being a second subset of the n bits forming said virtual address.

4 more elements

A cache memory system in a computing device having a processor, for responding to an n-bit virtual address having at least a virtual page number and a page offset, the system comprising:

a primary cache for storing words, said primary cache organized into a plurality of primary-cache lines, each primary-cache line for storing a primary-cache physical tag and a block of said words, wherein j words form a primary-cache block, each primary cache line being accessible in response to a virtual index, wherein said virtual index is a first subset of said n bit virtual address;
means for translating said n-bit virtual address to an m-bit physical address;
a secondary cache for storing words, said secondary cache organized into a plurality of secondary-cache lines, each secondary-cache line for storing a secondary-cache physical tag for identifying a physical address, a primary index segment for identifying a virtual address, and a block of said words, wherein k words form a secondary-cache block each secondary cache line being accessible in response to a physical index wherein said physical index is a first subset of said m-bit physical address;
means coupled to said primary cache for comparing a first select primary-cache physical tag stored in said primary cache with a primary-cache tag reference, wherein said primary-cache tag reference is a second subset of said m-bit physical address;
means coupled to said secondary cache for comparing a select secondary-cache physical tag stored in said secondary cache with a secondary-cache tag reference wherein said secondary-cache tag reference is a third subset of said m-bit physical address;
and
means for comparing a select primary index segment stored in said secondary cache and a primary index segment reference in response to a match between said select secondary-cache physical tag and said secondary-cache tag reference so to determine whether a word in said secondary cache is the word addressed by said n-bit virtual address wherein said primary index segment reference is a second subset of said n-bit virtual address.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/212,377Filed 11 Mar 1994 · continuation
Priority: 3 Apr 1991
Granted: 26 Dec 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/0897
Caches characterised by their organisation or structure: with two or more cache hierarchy levels
G06F 12/1054
Associated with a data cache: the data cache being concurrently physically addressed
G06F 12/0848
Cache with multiple tag or data arrays being simultaneously accessible: partitioned cache, e.g. separate instruction and operand caches
G06F
Computing and data processing