Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays

A processor, for use in a data processing system, which includes a bus and a memory coupled with said bus, comprising:

• a central processing unit for executing an instruction;
• a cache memory coupled to said central processing unit, for storing instructions;
• a memory management unit for converting a logical address received from said central processing unit into a physical address and for sending said physical address to said bus;
• a cache memory control circuit, coupled to said cache memory, for preventing data from being loaded into said cache memory in response to a control signal;
• and
• a circuit for generating said control signal in response to an access by said physical address on said bus from said memory management unit to a predetermined memory region in said memory.

A processor, for use in a data processing system which includes a bus and a memory coupled with said bus, comprising:

• a central processing unit for executing an instruction;
• a cache memory, coupled to said central processing unit, for storing instructions;
• a memory management unit for converting a logical address from said central processing unit into a physical address and for sending said physical address to said bus;
• and
• a cache memory control circuit, coupled to said cache memory, for preventing data from being loaded into said cache memory in response to a control signal generated by a circuit, coupled to said bus so as to receive said physical address on said bus, for generating said control signal in response to an access by said physical address on said bus from said memory management unit to a predetermined memory region in said memory.