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US 5,479,622 AGranted
Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system
AssigneeInternational Business Machines Corporation
InventorsGregory F. Grohoski, Randall D. Groves
Life of this patent
Estimating the term…
Abstract
A data processing system including a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction. when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set.
Claims35
A data processing system comprising:
- means for providing sequential clock cycles individually corresponding to single system computation cycles;
- means for storing a plurality of instructions in sequence within an instruction memory;
- means for selectively dispatching a plurality of instructions following the sequence in which the instructions were stored in the instruction memory during a single clock cycle to selected processors for execution;
- means for determining for each instruction to be dispatched by the means for dispatching whether that instruction may when executed be dependent upon a bit in a condition register characterizing a previous instruction result;
- means for monitoring the setting of said bit in said condition register and providing an indication thereof;
- and
- control means for selectively delaying the dispatch of one or more instructions during the clock cycle when said means for determining indicates that the instruction is dependent upon the setting of said bit and that said means for monitoring indicates that said bit has not been set.
4 more elements
A data processing system comprising:
- means for providing sequential clock cycles individually corresponding to single system computation cycles;
- means for storing a plurality of instructions in sequence within an instruction memory;
- means for selectively dispatching a plurality of instructions following the sequence in which the instructions were stored in the instruction memory during a single clock cycle to selected processors for execution;
- means for determining for each instruction to be dispatched by the means for dispatching whether that instruction may when executed set bit in a condition register to be accessed by a processor executing a previous instruction;
- means for monitoring the accessing of said bit in said condition register and providing an indication thereof;
- and
- control means for selectively delaying the dispatching of one or more instructions during the clock cycle when execution of a previous instruction has not accessed said bit in said condition register, as indicated by the means for determining.
4 more elements
A method for providing instructions in a data processing system comprising the computer implemented steps of:
- providing sequential clock cycles individually corresponding to single system computation cycles;
- storing a plurality of instructions in sequence within an instruction memory;
- dispatching a plurality of selected instructions following the sequence in which the instructions were stored in the instruction memory to selected processors during a single clock cycle;
- determining when an instruction execution is dependent upon a previous instruction setting a bit in a condition register characterizing a previous instruction result;
- monitoring the setting of said bit in the condition register and providing an indication thereof;
- and
- selectively delaying the dispatching of an instruction during the clock cycle the instruction is to be dispatched when there is an indication that the instruction is dependent upon the setting of said bit and that there is no indication that said bit has been set.
4 more elements
A method for providing instructions in a data processing system comprising the computer implemented steps of:
- providing sequential clock cycles individually corresponding to single system computation cycles;
- storing a plurality of instructions in sequence within an instruction memory;
- dispatching a plurality of selected instructions following the sequence in which the instructions were stored in the instruction memory to selected processors during a single clock cycle;
- determining for each instruction to be dispatched whether that instruction may when executed set a bit in a condition register to be accessed by a processor executing a previous instruction;
- monitoring the access of said bit in said condition register and providing an indication thereof;
- and
- selectively delaying the dispatching of an instruction during the clock cycle the instruction is to be dispatched when execution of a previous instruction has not accessed said bit in said condition register.
4 more elements
A data processing system comprising:
- means for providing sequential clock cycles individually corresponding to single system computation cycles;
- means for selectively dispatching in sequence a plurality of sequentially stored instructions from storage within an instruction memory during a single clock cycle to selected processors for execution;
- means for determining within a clock cycle whether instructions subject to dispatch may depend on settings in fields of a condition register, wherein the settings in the fields are related to previous instructions executing in processors;
- control means for selectively delaying the dispatch of an instruction during the clock cycle when said means for determining indicates that the instruction is dependent upon the setting of a condition register field that has not been set.
1 more element
A data processing system comprising:
- means for providing sequential clock cycles individually corresponding to single system computation cycles;
- means for selectively dispatching in sequence a plurality of sequentially stored instructions from storage within an instruction memory during a single clock cycle to selected processors for execution;
- means for determining within a clock cycle whether instructions subject to dispatch may when executed set a field of a condition register that is to be accessed by a processor executing a previous instruction;
- and
- control means for selectively delaying the dispatch of the instruction during the clock cycle when said means for determining indicates that the accessing of the condition field has not been accomplished.
2 more elements
A data processing system comprising:
- means for providing sequential clock cycles individually corresponding to single system computation cycles;
- an instruction memory for storing a plurality of instructions in sequence;
- means for fetching a plurality of instructions during a first clock cycle;
- at least one condition register related to multiple processors;
- and
- means for resolving dependencies reflected in the condition register and dispatching selected instructions in the sequence stored in the instruction memory to multiple processors for execution, during a second clock cycle following the first clock cycle.
3 more elements
A data processing system comprising:
- a clock providing clock cycles individually corresponding to single system computation cycles;
- a plurality off processors, each for independently executing instructions and indicating a condition code resulting from instruction execution;
- an instruction memory for storing a plurality of instructions in sequence;
- a condition register containing condition codes indications from at least two of said processors;
- and
- means for dispatching a plurality of instructions in the sequence stored in the instruction memory during a single clock cycle to at least two of said processors, said dispatching means including means for determining a condition code dependency for each instruction and having means for delaying the dispatching of any instruction having a condition code dependency.
3 more elements
A data processing system comprising:
- a clock providing clock cycles individually corresponding to single system computation cycles;
- a plurality of processors, each for independently executing instructions and indicating a condition code resulting from instruction execution;
- an instruction memory for storing a plurality of instructions in sequence;
- a register containing condition codes indications from at least two processors and including means indicating if said condition codes indications are valid;
- and
- means for dispatching a plurality of instructions in the sequence stored in the instruction memory during a single clock cycle to at least two of said processors when condition codes indications for each instruction are valid.
3 more elements
Dependencies are inferred from the claim text.