Solid state peripheral storage device having redundent mapping memory algorithm

A computer system having a computer with a solid state peripheral storage device with the computer providing a first address signal, and a data signal to the solid state peripheral storage device, said computer system comprising:

• a first memory means in the solid state peripheral storage device for storing the data signal from the computer, said first memory means comprising a plurality of floating gate storage cells;
• a second memory means in the solid state peripheral storage device for storing a plurality of second address signals, each of said plurality of second address signals is stored in duplicate in said second memory means, with one of said plurality of second address signals stored at a first location and with a duplicate of said one of said plurality of second address signals stored at a corresponding first location, each of said plurality of second address signals representing an address signal to the first memory means, said second memory means comprising a plurality of floating gate storage cells;
• a third memory means comprising a plurality of floating gate storage cells;
• said computer executing a program having means for addressing the second memory means based upon the first address signal, and to retrieve said one of said plurality of second address signals from said first location and said duplicate of said one of said plurality of second address signals from said corresponding first location and to address the first memory means in response thereto;
• and
• said computer executing the program further having means for detecting defects in the second memory means at said first location;
• and for changing the second memory means at said corresponding first location to store an indirect address signal;
• said indirect address signal addressing a second location in the third memory means;
• and for storing the one of said plurality of second address signals from the corresponding first location in the third memory means, at said second location.

A computer system having a computer with a solid state peripheral storage device with the computer providing a first address signal and a data signal to the solid state peripheral storage device, said computer system comprising:

• memory means in the solid state peripheral storage device comprising a plurality of floating gate storage cells and having
• a first portion for storing the data signal from the computer;
• or for retrieving data signal stored therein to be supplied to the computer;
• a second portion for storing a plurality of second address signals, wherein each of said plurality of second address signals is stored in duplicate in said second portion, with each of said plurality of second address signals stored at a location and with a duplicate of said each of said plurality of second address signals stored at a corresponding location, said plurality of second address signals representing address signals to the first portion of the memory means;
• a third portion;
• said computer executing a program having means for addressing the second portion of the memory means based upon the first address signal, and to retrieve one of said plurality of second address signals therefrom and to address the first portion of the memory means based upon the one of said plurality of second address signals retrieved from the second portion;
• and
• said computer executing a program further having means for detecting one or more defects in the second portion of the memory means at a first location addressed by the first address signal;
• and for changing the second portion of the memory means at a corresponding first location to store an indirect address signal;
• said indirect address signal addressing a second location in the third portion of the memory means;
• and for storing the one of said plurality of second address signals from the corresponding first location, at said second location.

A method of reading data signals from or writing data signals to a solid state peripheral storage device connected to a computer, said method comprising:

• supplying a first address signal from the computer to the solid state peripheral storage device;
• reading a plurality of second address signals stored in a memory means having a plurality of floating gate storage cells, from a plurality of first locations based upon the first address signal;
• determining if one of said plurality of second address signals from said plurality of first locations is in error;
• and
• in an event of an error;
• writing one of said plurality of second address signals, from one of said plurality of first locations which is not in error, into another portion of the memory means, at a second location;
• writing an indirect address signal into said one of said plurality of first locations, said indirect address signal representing an address signal to said another portion of the memory means, at said second location;
• addressing said memory means with said first address signal to retrieve said indirect address signal;
• addressing said memory means with said indirect address signal to retrieve said one of said plurality of second address signals;
• and
• addressing said memory means with said one of said plurality of second address signals to read data signals therefrom or to write data signals thereto.