Weighted summation circuitry with digitally controlled capacitive structures

An integrated-circuit having therewithin:

• an array of weighted summation circuits, N in number, each weighted summation circuit capable of generating a respective weighted sum response to a common plurality of input signals, M in number, said input signals corresponding to respective ones of consecutive ordinal numbers first through M.sup.th, said weighted summation circuits corresponding to respective ones of consecutive ordinal numbers first through N.sup.th, the respective weighted sum response generated by each of said weighted summation circuits being identified by an ordinal number identifying said weighted summation circuit respectively generating said ordinal number;
• an array of word storage elements, M times N in number, M being an integer more than one and N being an integer more than one, each word storage element for temporarily storing a respective digital word descriptive of a weighting to be afforded by said array of weighted summation circuits to one of said first through M.sup.th input signals in generating one of said first through N.sup.th weighted sum responses;
• and
• within each of first through N.sup.th said weighted summation circuits, at least one corresponding capacitive element for determining the weighting of each of said first through M.sup.th input signals of a type having its capacitance value determined incrementally in accordance with bits of the respective digital word descriptive of that weighting, as temporarily stored in said array of word storage elements.