Zigzag scanning address generator and method therefor

A zigzag scanning address generator comprising:

• row address generating means for generating row address signal which stops, increases and decreases a present state in response to an enabling signal, said row address generating means comprising:
• row state storing and decoding means for responding to said enabling signal by receiving a next row state signal and thereby decoding said next row state signal, said row state storing and decoding means including:
• first and second flip-flops having a reset port reset by said enabling signal and a set port connected to ground, for respectively receiving the output signal of said next row state generator to the data input ports thereto;
• first AND-operating means for performing an AND-operation with respect to the inverted output signals of said first and second flip-flops;
• second AND-operating means for performing an AND-operation with respect to the output signal of said first flip-flop and the inverted output signal of said second flip-flop;
• and
• third AND-operating means for performing an AND-operation with respect to the inverted output signal of said first flip-flop and the output signal of said second flip-flop;
• row up/down counting means for up/down-counting the output signal of said row state storing and decoding means in response thereto, and generating a row address signal, said row up/down counting means comprising:
• a row up/down counter for counting the output signal of said second AND-operating means in response thereto, having a hold port which receives the output signal of said first AND-operating means and an up/down port which receives the output signal of said second AND-operating means, to thereby generate a 3-bit row address signal;
• and
• a row decoder for decoding the output signal of said row up/down counter;
• and
• next row state generating means for generating a next row state signal by receiving output signals of said row state storing and decoding means, the output signals of said row up/down counting means, and the column address signals;
• and
• column address generating means for generating column address signal which stops, increases and decreases a present state in response to said enabling signal, said column address generating means comprising:
• column state storing and decoding means for responding to said enabling signal, receiving a next column state signal and thereby decoding said next column state signal, said column state storing and decoding means comprises:
• a third flip-flop for receiving a first output signal of said next row state generator at the data input port thereto, with its set port being set by said enabling signal and its reset port being connected to ground;
• a fourth flip-flop for receiving a second output signal of said next row state generator at the data input port thereto, with its reset port being reset by said enabling signal and its set port being to ground;
• fourth AND-operating means for performing an AND-operation with respect to the inverted output signals of said third and fourth flip-flops;
• fifth AND-operating means for performing an AND-operation with respect to the output signal of said third flip-flop and the inverted output signal of said fourth flip-flop;
• and
• sixth AND-operating means for performing an AND-operation with respect to the inverted output signal of said third flip-flop and the output signal of said fourth flip-flop;
• column up/down counting means for up/down-counting the output signal of said column state storing and decoding means in response thereto and generating a column address signal, said column up/down counting means comprising:
• a column up/down counter for counting the output signal of said second AND-operating means in response thereto, having a hold port which receives the output signal of said first AND-operating means and an up/down port which receives the output signal of said second AND-operating means, to thereby generate a 3-bit column address signal;
• and a column decoder for decoding the output signal of said column up/down counter;
• and
• next column state generating means for generating a next column state signal by receiving the output signal of said column state storing and decoding means and the output signals of said column up/down counting means and column address signals.