Clock fault monitoring circuit

Abstract

A circuit for determining whether a digital circuit clock is operating normally. It includes a monitoring clock receiver for receiving a monitoring clock signal, a counter reset generator which generates a first reset signal in response to the monitoring clock signal, and a reset signal receiver for receiving a second reset signal and synchronizing the second reset signal with the monitoring clock signal. The second reset signal is also used to initialize a digital circuit pack upon power-on. The circuit further includes a monitoring counter circuit for sampling and counting a reference clock signal in response to the first and second reset signals to monitor the monitoring clock signal. The reference clock signal has a frequency twice that of the monitoring clock signal. A NAND logic unit is provided for outputting the monitored result in response to an output signal from the monitoring counter circuit so that the user can determine a clock error according to the monitored result. An output hold circuit is further provided for holding the monitored result from the NAND logic unit when the monitoring clock signal is abnormal.

Dependencies are inferred from the claim text.