Method and apparatus for generating test pulses

A test system for both generating product-specific digital test signals, and addressing and predetermining test data and test functions from data signals and timing signals, wherein the test signals for predetermining test data comprise a test pulse occurring during a pulse interval, wherein the data signals associated with the test signals for each pulse interval comprise data for address, test pulse and function generation, wherein the timing signals for each pulse interval comprise information associated with the data signals, which denotes the start and end of address, test data and function generation in the respective test signals, comprising:

• a) addressable format memory means, coupled to receive the data signals, for storing different test signal formats for each data signal, wherein each particular test signal format denoting a binary voltage curve of voltage levels in a predetermined order of a test signal during a pulse interval;
• b) test pulse means for supplying format-specific adjacent signals of the same or a different level;
• c) address means coupled to the addressable format memory means, stores the format-specific adjacent signals as digital values denoting the binary voltage curve unrelated in time for each test signal format;
• d) reading means for reading the digital values denoting the binary voltage curve for each pulse interval at an output of the addressable format memory means on a number of lines corresponding to a number of level changes in the binary voltage curve;
• e) generating means for generating timing signals from digitally stored values denoting a time curve of the test signals;
• and
• f) bistable flip-flop means for generating a product spacific digital test signal and having a signal delay that is controlled by the timing signals from said generating means and coupled to said reading means to combine with the addressable format memory means output information for the test signal format associated with that data signal in the order of the level changes in the binary voltage curve for generating the test signal.

A test signal generating circuit, comprising:

• a) test signal generating means for generating a plurality of test signals that are unrelated to time, and for generating a timer start signal;
• b) timer signal generating means for generating a plurality of timing signals in response to receiving the start timer signal;
• and
• c) logic means, coupled to receive both the plurality of test signals and the plurality of timing signals, for generating a resultant test signal to be sent to a product under test;
• wherein the test signal generating means comprises:
• d) an addressable format memory circuit that generates a plurality of formatted coded test signals from a data signal and a program control signal;
• e) a format predecoder circuit that both moves the plurality of formatted coded test signals to the correct busses, and generates the timer start signal;
• and
• f) a format pipeline circuit that both variably delays the formatted coded test signals, and outputs the plurality of formatted coded test signals that are unrelated to time.

A test signal generating circuit, comprising:

• a) test signal generating means for generating a plurality of test signals that are unrelated to time, and for generating a timer start signal;
• b) timer signal generating means for generating a plurality of timing signals in response to receiving the start timer signal;
• and
• c) logic means, coupled to receive both the plurality of test signals and the plurality of timing signals, for generating a resultant test signal to be sent to a product under test;
• wherein the test signal generating means comprises:
• d) a signal generator, coupled to receive a program control signal, for generating a first signal;
• and
• e) a format processor circuit, coupled to receive the program control signal and the first signal, for generating both the timer start signal and the plurality of test signals that are unrelated to time.

A signal testing circuit, comprising:

• a) a pulse interval generator for generating a pulse signal;
• b) a signal generator, coupled to receive the pulse signal, for generating an address data signal, a data signal, and a write control data signal;
• c) a format processor circuit, including:
• c1) an address format processor circuit, coupled to receive the address data signal for generating an address timer start signal and a set of address format information signals;
• c2) a data format processor circuit, coupled to receive the data signal for generating a data timer start signal and a set of data format information signals;
• and
• c3) a write control format processor circuit, coupled to receive the write control data signal for generating a write control timer start signal and a set of write control format information signals;
• d) a timer circuit, including:
• d1) an address timer, coupled to receive the pulse signal and the address timer start signal, for generating a set of address timing signals;
• d2) a data timer, coupled to receive the pulse signal and the data timer start signal, for generating a set of data timing signals;
• and
• d3) a write control timer, coupled to receive the pulse signal and the write control timer start signal, for generating a set of write control timing signals;
• and
• e) a logic circuit, including:
• e1) address logic means, coupled to receive the set of address format information signals and the set of address timing signals, for generating an address test signal;
• e2) data logic means, coupled to receive the set of address format information signals and the set of data timing signals, for generating a data test signal;
• and
• e3) write control logic means, coupled to receive the set of address format information signals and the set of write control timing signals, for generating a write test signal.