Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing

A look ahead pattern generation and simulation method performed by a tester apparatus which includes a pattern generator that generates VLSI "scan path" test patterns, known as "tester loops", said method comprising the steps of:

• simulating a test of a device under test by said tester apparatus by using a plurality of tester loops generated by said pattern generator, to provide results of said step of simulating;
• analyzing said results of said step of simulating to determine which tester loops are effective and which tester loops are ineffective to provide a meaningful test result output;
• marking each of said plurality of said tester loops as effective or ineffective based on said analyzing step;
• loading marked tester loops into said tester apparatus, said marked tester loops being for test pattern application on the device under test;
• for each tester loop of said plurality of tester loops loaded into the tester apparatus, saving a current state of the pattern generator in a register;
• prior to applying a tester loop of said plurality of tester loops to the device under test, checking the tester loop to determine if the tester loop is marked as effective or ineffective;
• if the tester loop is marked as effective, applying the tester loop from the pattern generator to the device under test, restoring the current pattern generator state by reading a saved current state stored in said register, and advancing the pattern generator one state;
• but
• if the tester loop is marked as ineffective, advancing the pattern generator one state to skip the tester loop, thereby increasing throughput of the tester apparatus.